drm/radeon/dpm: fix fallback for empty UVD clocks

Some older 6xx-7xx boards didn't always fill in the
UVD clocks properly in the UVD power states.  This
leads to the driver trying to set a 0 clock which
results in slow or broken UVD playback.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=69120

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/radeon/rs780_dpm.c b/drivers/gpu/drm/radeon/rs780_dpm.c
index 625d6ea..828a776 100644 (file)
--- a/drivers/gpu/drm/radeon/rs780_dpm.c
+++ b/drivers/gpu/drm/radeon/rs780_dpm.c
@@ -726,14 +726,18 @@ static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev,
        if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
                rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
                rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
-       } else if (r600_is_uvd_state(rps->class, rps->class2)) {
-               rps->vclk = RS780_DEFAULT_VCLK_FREQ;
-               rps->dclk = RS780_DEFAULT_DCLK_FREQ;
        } else {
                rps->vclk = 0;
                rps->dclk = 0;
        }
 
+       if (r600_is_uvd_state(rps->class, rps->class2)) {
+               if ((rps->vclk == 0) || (rps->dclk == 0)) {
+                       rps->vclk = RS780_DEFAULT_VCLK_FREQ;
+                       rps->dclk = RS780_DEFAULT_DCLK_FREQ;
+               }
+       }
+
        if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
                rdev->pm.dpm.boot_ps = rps;
        if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)

diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c
index 8cbb85d..7282ce7 100644 (file)
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -2147,14 +2147,18 @@ static void rv7xx_parse_pplib_non_clock_info(struct radeon_device *rdev,
        if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
                rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
                rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
-       } else if (r600_is_uvd_state(rps->class, rps->class2)) {
-               rps->vclk = RV770_DEFAULT_VCLK_FREQ;
-               rps->dclk = RV770_DEFAULT_DCLK_FREQ;
        } else {
                rps->vclk = 0;
                rps->dclk = 0;
        }
 
+       if (r600_is_uvd_state(rps->class, rps->class2)) {
+               if ((rps->vclk == 0) || (rps->dclk == 0)) {
+                       rps->vclk = RV770_DEFAULT_VCLK_FREQ;
+                       rps->dclk = RV770_DEFAULT_DCLK_FREQ;
+               }
+       }
+
        if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
                rdev->pm.dpm.boot_ps = rps;
        if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)