bool isV0Reg() const {
return Kind == KindTy::Register && Reg.RegNum == RISCV::V0;
}
+ bool isAnyReg() const {
+ return Kind == KindTy::Register &&
+ (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum) ||
+ RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg.RegNum) ||
+ RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg.RegNum));
+ }
bool isImm() const override { return Kind == KindTy::Immediate; }
bool isMem() const override { return false; }
bool isSystemRegister() const { return Kind == KindTy::SystemRegister; }
// .insn directive instructions
//===----------------------------------------------------------------------===//
+def AnyRegOperand : AsmOperandClass {
+ let Name = "AnyRegOperand";
+ let RenderMethod = "addRegOperands";
+ let PredicateMethod = "isAnyReg";
+}
+
+def AnyReg : Operand<XLenVT> {
+ let OperandType = "OPERAND_REGISTER";
+ let ParserMatchClass = AnyRegOperand;
+}
+
// isCodeGenOnly = 1 to hide them from the tablegened assembly parser.
let isCodeGenOnly = 1, hasSideEffects = 1, mayLoad = 1, mayStore = 1,
hasNoSchedulingInfo = 1 in {
// Special registers
def FFLAGS : RISCVReg<0, "fflags">;
def FRM : RISCVReg<0, "frm">;
-
-// Any type register. Used for .insn directives when we don't know what the
-// register types could be.
-// NOTE: The alignment and size are bogus values. The Size needs to be non-zero
-// or tablegen will use "untyped" to determine the size which will assert.
-let isAllocatable = 0 in
-def AnyReg : RegisterClass<"RISCV", [untyped], 32,
- (add (sequence "X%u", 0, 31),
- (sequence "F%u_D", 0, 31),
- (sequence "V%u", 0, 31))> {
- let Size = 32;
-}