ARM: DT: stm32f7: add usart1 & clock device tree nodes
authorVikas Manocha <vikas.manocha@st.com>
Sun, 12 Feb 2017 18:25:47 +0000 (10:25 -0800)
committerTom Rini <trini@konsulko.com>
Fri, 17 Mar 2017 18:15:13 +0000 (14:15 -0400)
Also created alias for usart1 and specified oscillator clock for stm32f7
discovery board.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
arch/arm/dts/stm32f746-disco.dts
arch/arm/dts/stm32f746.dtsi

index bad0698..454b515 100644 (file)
        };
 
        aliases {
+               serial0 = &usart1;
                spi0 = &qspi;
        };
 };
 
+&clk_hse {
+       clock-frequency = <25000000>;
+};
+
 &mac {
        status = "okay";
        phy-mode = "rmii";
index 3902e76..afcd327 100644 (file)
 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
 
 / {
+       clocks {
+               clk_hse: clk-hse {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <0>;
+               };
+};
+
        soc {
+               u-boot,dm-pre-reloc;
                mac: ethernet@40028000 {
                        compatible = "st,stm32-dwmac";
                        reg = <0x40028000 0x8000>;
                        spi-max-frequency = <108000000>;
                        status = "disabled";
                };
+               usart1: serial@40011000 {
+                       compatible = "st,stm32-usart", "st,stm32-uart";
+                       reg = <0x40011000 0x400>;
+                       interrupts = <37>;
+                       clocks = <&rcc 0 164>;
+                       status = "disabled";
+                       u-boot,dm-pre-reloc;
+               };
+               rcc: rcc@40023810 {
+                       #reset-cells = <1>;
+                       #clock-cells = <2>;
+                       compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+                       reg = <0x40023800 0x400>;
+                       clocks = <&clk_hse>;
+                       u-boot,dm-pre-reloc;
+               };
+
+
        };
 };