dmaengine: xilinx_dma: Program interrupt delay timeout

Program IRQDelay for AXI DMA. The interrupt timeout mechanism causes
the DMA engine to generate an interrupt after the delay time period
has expired. It enables dmaengine to respond in real-time even though
interrupt coalescing is configured. It also remove the placeholder
for delay interrupt and merge it with frame completion interrupt.
Since by default interrupt delay timeout is disabled this feature
addition has no functional impact on VDMA, MCDMA and CDMA IP's.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Link: https://lore.kernel.org/r/1691387509-2113129-8-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index ccd02d8..0a3b2e2 100644 (file)
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -173,8 +173,10 @@
 #define XILINX_DMA_MAX_TRANS_LEN_MAX   23
 #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX        26
 #define XILINX_DMA_CR_COALESCE_MAX     GENMASK(23, 16)
+#define XILINX_DMA_CR_DELAY_MAX                GENMASK(31, 24)
 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK        BIT(4)
 #define XILINX_DMA_CR_COALESCE_SHIFT   16
+#define XILINX_DMA_CR_DELAY_SHIFT      24
 #define XILINX_DMA_BD_SOP              BIT(27)
 #define XILINX_DMA_BD_EOP              BIT(26)
 #define XILINX_DMA_BD_COMP_MASK                BIT(31)
@@ -411,6 +413,7 @@ struct xilinx_dma_tx_descriptor {
  * @stop_transfer: Differentiate b/w DMA IP's quiesce
  * @tdest: TDEST value for mcdma
  * @has_vflip: S2MM vertical flip
+ * @irq_delay: Interrupt delay timeout
  */
 struct xilinx_dma_chan {
        struct xilinx_dma_device *xdev;
@@ -449,6 +452,7 @@ struct xilinx_dma_chan {
        int (*stop_transfer)(struct xilinx_dma_chan *chan);
        u16 tdest;
        bool has_vflip;
+       u8 irq_delay;
 };
 
 /**
@@ -1561,6 +1565,9 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
        if (chan->has_sg)
                xilinx_write(chan, XILINX_DMA_REG_CURDESC,
                             head_desc->async_tx.phys);
+       reg  &= ~XILINX_DMA_CR_DELAY_MAX;
+       reg  |= chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT;
+       dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
 
        xilinx_dma_start(chan);
 
@@ -1898,15 +1905,8 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, void *data)
                }
        }
 
-       if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) {
-               /*
-                * Device takes too long to do the transfer when user requires
-                * responsiveness.
-                */
-               dev_dbg(chan->dev, "Inter-packet latency too long\n");
-       }
-
-       if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) {
+       if (status & (XILINX_DMA_DMASR_FRM_CNT_IRQ |
+                     XILINX_DMA_DMASR_DLY_CNT_IRQ)) {
                spin_lock(&chan->lock);
                xilinx_dma_complete_descriptor(chan);
                chan->idle = true;
@@ -2833,6 +2833,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
        /* Retrieve the channel properties from the device tree */
        has_dre = of_property_read_bool(node, "xlnx,include-dre");
 
+       of_property_read_u8(node, "xlnx,irq-delay", &chan->irq_delay);
+
        chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode");
 
        err = of_property_read_u32(node, "xlnx,datawidth", &value);