net/mlx5: Dynamic cyclecounter shift calculation for PTP free running clock

Use a dynamic calculation to determine the shift value for the internal
timer cyclecounter that will lead to the highest precision frequency
adjustments. Previously used a constant for the shift value assuming all
devices supported by the driver had a nominal frequency of 1GHz. However,
there are devices that operate at different frequencies. The previous shift
value constant would break the PHC functionality for those devices.

Reported-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>
Closes: https://lore.kernel.org/netdev/20230815151507.3028503-1-vadfed@meta.com/
Fixes: 6a4010927562 ("net/mlx5: Update cyclecounter shift value to improve ptp free running mode precision")
Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Tested-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>
Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Acked-by: Saeed Mahameed <saeedm@nvidia.com>
Link: https://lore.kernel.org/r/20230821230554.236210-1-rrameshbabu@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
index 377372f..aa29f09 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
@@ -32,6 +32,7 @@
 
 #include <linux/clocksource.h>
 #include <linux/highmem.h>
+#include <linux/log2.h>
 #include <linux/ptp_clock_kernel.h>
 #include <rdma/mlx5-abi.h>
 #include "lib/eq.h"
@@ -39,10 +40,6 @@
 #include "clock.h"
 
 enum {
-       MLX5_CYCLES_SHIFT       = 31
-};
-
-enum {
        MLX5_PIN_MODE_IN                = 0x0,
        MLX5_PIN_MODE_OUT               = 0x1,
 };
@@ -93,6 +90,31 @@ static bool mlx5_modify_mtutc_allowed(struct mlx5_core_dev *mdev)
        return MLX5_CAP_MCAM_FEATURE(mdev, ptpcyc2realtime_modify);
 }
 
+static u32 mlx5_ptp_shift_constant(u32 dev_freq_khz)
+{
+       /* Optimal shift constant leads to corrections above just 1 scaled ppm.
+        *
+        * Two sets of equations are needed to derive the optimal shift
+        * constant for the cyclecounter.
+        *
+        *    dev_freq_khz * 1000 / 2^shift_constant = 1 scaled_ppm
+        *    ppb = scaled_ppm * 1000 / 2^16
+        *
+        * Using the two equations together
+        *
+        *    dev_freq_khz * 1000 / 1 scaled_ppm = 2^shift_constant
+        *    dev_freq_khz * 2^16 / 1 ppb = 2^shift_constant
+        *    dev_freq_khz = 2^(shift_constant - 16)
+        *
+        * then yields
+        *
+        *    shift_constant = ilog2(dev_freq_khz) + 16
+        */
+
+       return min(ilog2(dev_freq_khz) + 16,
+                  ilog2((U32_MAX / NSEC_PER_MSEC) * dev_freq_khz));
+}
+
 static s32 mlx5_ptp_getmaxphase(struct ptp_clock_info *ptp)
 {
        struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
@@ -909,7 +931,7 @@ static void mlx5_timecounter_init(struct mlx5_core_dev *mdev)
 
        dev_freq = MLX5_CAP_GEN(mdev, device_frequency_khz);
        timer->cycles.read = read_internal_timer;
-       timer->cycles.shift = MLX5_CYCLES_SHIFT;
+       timer->cycles.shift = mlx5_ptp_shift_constant(dev_freq);
        timer->cycles.mult = clocksource_khz2mult(dev_freq,
                                                  timer->cycles.shift);
        timer->nominal_c_mult = timer->cycles.mult;