}
}
-unsigned RegisterFile::isAvailable(const ArrayRef<unsigned> Regs) const {
+unsigned RegisterFile::isAvailable(ArrayRef<unsigned> Regs) const {
SmallVector<unsigned, 4> NumTemporaries(getNumRegisterFiles());
// Find how many new mappings must be created for each register file.
// For example: if all register files are available, then the response mask
// is a bitmask of all zeroes. If Instead register file #1 is not available,
// then the response mask is 0b10.
- unsigned isAvailable(const llvm::ArrayRef<unsigned> Regs) const;
+ unsigned isAvailable(llvm::ArrayRef<unsigned> Regs) const;
void collectWrites(llvm::SmallVectorImpl<WriteState *> &Writes,
unsigned RegID) const;
void updateOnRead(ReadState &RS, unsigned RegID);
LastGenericEventType,
};
- HWInstructionEvent(unsigned Type, unsigned Index)
- : Type(Type), Index(Index) {}
+ HWInstructionEvent(unsigned type, unsigned index)
+ : Type(type), Index(index) {}
// The event type. The exact meaning depends on the subtarget.
const unsigned Type;
public:
using ResourceRef = std::pair<uint64_t, uint64_t>;
HWInstructionIssuedEvent(
- unsigned Index, const llvm::ArrayRef<std::pair<ResourceRef, unsigned>> UR)
+ unsigned Index, llvm::ArrayRef<std::pair<ResourceRef, unsigned>> UR)
: HWInstructionEvent(HWInstructionEvent::Issued, Index),
UsedResources(UR) {}
- const llvm::ArrayRef<std::pair<ResourceRef, unsigned>> UsedResources;
+ llvm::ArrayRef<std::pair<ResourceRef, unsigned>> UsedResources;
};
// A HWStallEvent represents a pipeline stall caused by the lack of hardware
static void
initializeUsedResources(InstrDesc &ID, const MCSchedClassDesc &SCDesc,
const MCSubtargetInfo &STI,
- const ArrayRef<uint64_t> ProcResourceMasks) {
+ ArrayRef<uint64_t> ProcResourceMasks) {
const MCSchedModel &SM = STI.getSchedModel();
// Populate resources consumed.
}
ResourceStateEvent
-ResourceManager::canBeDispatched(const ArrayRef<uint64_t> Buffers) const {
+ResourceManager::canBeDispatched(ArrayRef<uint64_t> Buffers) const {
ResourceStateEvent Result = ResourceStateEvent::RS_BUFFER_AVAILABLE;
for (uint64_t Buffer : Buffers) {
Result = isBufferAvailable(Buffer);
return Result;
}
-void ResourceManager::reserveBuffers(const ArrayRef<uint64_t> Buffers) {
+void ResourceManager::reserveBuffers(ArrayRef<uint64_t> Buffers) {
for (const uint64_t R : Buffers) {
reserveBuffer(R);
ResourceState &Resource = *Resources[R];
}
}
-void ResourceManager::releaseBuffers(const ArrayRef<uint64_t> Buffers) {
+void ResourceManager::releaseBuffers(ArrayRef<uint64_t> Buffers) {
for (const uint64_t R : Buffers)
releaseBuffer(R);
}
}
void Scheduler::notifyInstructionIssued(
- unsigned Index, const ArrayRef<std::pair<ResourceRef, unsigned>> &Used) {
+ unsigned Index, ArrayRef<std::pair<ResourceRef, unsigned>> Used) {
DEBUG({
dbgs() << "[E] Instruction Issued: " << Index << '\n';
for (const std::pair<ResourceRef, unsigned> &Resource : Used) {
// Consume a slot in every buffered resource from array 'Buffers'. Resource
// units that are dispatch hazards (i.e. BufferSize=0) are marked as reserved.
- void reserveBuffers(const llvm::ArrayRef<uint64_t> Buffers);
+ void reserveBuffers(llvm::ArrayRef<uint64_t> Buffers);
// Release buffer entries previously allocated by method reserveBuffers.
- void releaseBuffers(const llvm::ArrayRef<uint64_t> Buffers);
+ void releaseBuffers(llvm::ArrayRef<uint64_t> Buffers);
void reserveResource(uint64_t ResourceID) {
ResourceState &Resource = *Resources[ResourceID];
void notifyInstructionIssued(
unsigned Index,
- const llvm::ArrayRef<std::pair<ResourceRef, unsigned>> &Used);
+ llvm::ArrayRef<std::pair<ResourceRef, unsigned>> Used);
void notifyInstructionExecuted(unsigned Index);
void notifyInstructionReady(unsigned Index);
void notifyResourceAvailable(const ResourceRef &RR);