arm64: dts: mediatek: Add cpufreq nodes for MT8192

[ Upstream commit 9d498cce9298a71e3896e2d1aee24a1a4c531d81 ]

Add the cpufreq nodes for MT8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230317061944.15434-1-allen-kh.cheng@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Stable-dep-of: a4366b5695c9 ("arm64: dts: mediatek: mt8192: Fix CPUs capacity-dmips-mhz")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index ef1294d..ff2310f 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -64,6 +64,7 @@
                        clock-frequency = <1701000000>;
                        cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
                        next-level-cache = <&l2_0>;
+                       performance-domains = <&performance 0>;
                        capacity-dmips-mhz = <530>;
                };
 
@@ -75,6 +76,7 @@
                        clock-frequency = <1701000000>;
                        cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
                        next-level-cache = <&l2_0>;
+                       performance-domains = <&performance 0>;
                        capacity-dmips-mhz = <530>;
                };
 
@@ -86,6 +88,7 @@
                        clock-frequency = <1701000000>;
                        cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
                        next-level-cache = <&l2_0>;
+                       performance-domains = <&performance 0>;
                        capacity-dmips-mhz = <530>;
                };
 
@@ -97,6 +100,7 @@
                        clock-frequency = <1701000000>;
                        cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
                        next-level-cache = <&l2_0>;
+                       performance-domains = <&performance 0>;
                        capacity-dmips-mhz = <530>;
                };
 
@@ -108,6 +112,7 @@
                        clock-frequency = <2171000000>;
                        cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
                        next-level-cache = <&l2_1>;
+                       performance-domains = <&performance 1>;
                        capacity-dmips-mhz = <1024>;
                };
 
@@ -119,6 +124,7 @@
                        clock-frequency = <2171000000>;
                        cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
                        next-level-cache = <&l2_1>;
+                       performance-domains = <&performance 1>;
                        capacity-dmips-mhz = <1024>;
                };
 
@@ -130,6 +136,7 @@
                        clock-frequency = <2171000000>;
                        cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
                        next-level-cache = <&l2_1>;
+                       performance-domains = <&performance 1>;
                        capacity-dmips-mhz = <1024>;
                };
 
@@ -141,6 +148,7 @@
                        clock-frequency = <2171000000>;
                        cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
                        next-level-cache = <&l2_1>;
+                       performance-domains = <&performance 1>;
                        capacity-dmips-mhz = <1024>;
                };
 
@@ -257,6 +265,12 @@
                compatible = "simple-bus";
                ranges;
 
+               performance: performance-controller@11bc10 {
+                       compatible = "mediatek,cpufreq-hw";
+                       reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+                       #performance-domain-cells = <1>;
+               };
+
                gic: interrupt-controller@c000000 {
                        compatible = "arm,gic-v3";
                        #interrupt-cells = <4>;