v4l2: add mipi pipeline support

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 554d7e3..f83a6d9 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -74,7 +74,7 @@
 &uart3 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart3_pins>;
-       status = "okay";
+       status = "disabled";
 };
 
 &dma {
@@ -233,6 +233,7 @@
                reg = <0x36>;
                clocks = <&clk_ext_camera>;
                clock-names = "xclk";
+               reset-gpio = <&gpio 18 0>;
                rotation = <180>;
 
                port {
@@ -241,7 +242,7 @@
                                remote-endpoint = <&csi2rx0_from_ov4689>;
                                bus-type = <4>;         /* MIPI CSI-2 D-PHY */
                                clock-lanes = <0>;
-                               data-lanes = <1 2>;
+                               data-lanes = <1 2 3 4>;
                        };
                };
        };
@@ -251,8 +252,7 @@
                reg = <0x10>;
                clocks = <&clk_ext_camera>;
                clock-names = "xclk";
-               powerdown-gpio = <&gpio 15 0>;
-               reset-gpio = <&gpio 16 0>;
+               //reset-gpio = <&gpio 18 0>;
                rotation = <0>;
 
                port {
@@ -278,7 +278,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&sdcard_pins>;
        //cd-gpios = <&gpio 23 0>;
-       status = "okay";
+       status = "disabled";
 };
 
 &sdio1 {
@@ -296,7 +296,7 @@
        post-power-on-delay-ms = <200>;
        pinctrl-names = "default";
        pinctrl-0 = <&mmc1_pins>;
-       status = "okay";
+       status = "disabled";
 };
 
 &vin_sysctl {
@@ -344,8 +344,8 @@
                                reg = <1>;
                                remote-endpoint = <&ov4689_to_csi2rx0>;
                                bus-type = <4>;      /* MIPI CSI-2 D-PHY */
-                               clock-lanes = <2>;
-                               data-lanes = <0 1>;
+                               clock-lanes = <0>;
+                               data-lanes = <1 2 3 4>;
                                status = "okay";
                        };
                };
@@ -390,7 +390,7 @@
 &can0 {
        pinctrl-names = "default";
        pinctrl-0 = <&can0_pins>;
-       status = "okay";
+       status = "disabled";
 };
 
 &can1 {
@@ -400,7 +400,7 @@
 &tdm {
        pinctrl-names = "default";
        pinctrl-0 = <&tdm0_pins>;
-       status = "okay";
+       status = "disabled";
 };
 
 &spdif0 {
@@ -436,7 +436,7 @@
 &i2stx_4ch1 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2s_clk_pins &i2stx_pins>;
-       status = "okay";
+       status = "disabled";
 };
 
 &ptc {

diff --git a/drivers/media/platform/starfive/v4l2_driver/ov4689_mipi.c b/drivers/media/platform/starfive/v4l2_driver/ov4689_mipi.c
index 9367d02..9b07cad 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/ov4689_mipi.c
+++ b/drivers/media/platform/starfive/v4l2_driver/ov4689_mipi.c
@@ -62,9 +62,9 @@
 
 
 enum ov4689_mode_id {
-       OV4689_MODE_720P_1280_720 = 0,
-       OV4689_MODE_1080P_1920_1080,
-       OV4689_MODE_4M_2688_1520,
+       //OV4689_MODE_720P_1280_720 = 0,
+       OV4689_MODE_1080P_1920_1080 = 0,
+       //OV4689_MODE_4M_2688_1520,
        OV4689_NUM_MODES,
 };
 
@@ -1533,11 +1533,7 @@ static const struct reg_value ov4689_setting_4M_2688_1520[] = {
 
 /* power-on sensor init reg table */
 static const struct ov4689_mode_info ov4689_mode_init_data = {
-       OV4689_MODE_1080P_1920_1080, SCALING,
-       1920, 0x6e0, 1080, 0x470,
-       ov4689_init_setting_30fps_1080P,
-       ARRAY_SIZE(ov4689_init_setting_30fps_1080P),
-       OV4689_60_FPS,
+
 };
 
 static const struct ov4689_mode_info
@@ -1557,6 +1553,12 @@ ov4689_mode_data[OV4689_NUM_MODES] = {
        //  ov4689_setting_4M_2688_1520,
        //  ARRAY_SIZE(ov4689_setting_4M_2688_1520),
        //  OV4689_60_FPS},
+
+       {OV4689_MODE_1080P_1920_1080, SCALING,
+        1920, 0x6e0, 1080, 0x470,
+        ov4689_init_setting_30fps_1080P,
+        ARRAY_SIZE(ov4689_init_setting_30fps_1080P),
+        OV4689_60_FPS},
 };
 
 static int ov4689_write_reg(struct ov4689_dev *sensor, u16 reg, u8 val)
@@ -1663,8 +1665,6 @@ static int ov4689_mod_reg(struct ov4689_dev *sensor, u16 reg,
 static int ov4689_set_timings(struct ov4689_dev *sensor,
                        const struct ov4689_mode_info *mode)
 {
-       int ret;
-
        return 0;
 }
 
@@ -2164,6 +2164,7 @@ power_off:
 
 static int ov4689_s_power(struct v4l2_subdev *sd, int on)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
        struct ov4689_dev *sensor = to_ov4689_dev(sd);
        int ret = 0;
 
@@ -2751,6 +2752,7 @@ static int ov4689_stream_start(struct ov4689_dev *sensor, int enable)
 
 static int ov4689_s_stream(struct v4l2_subdev *sd, int enable)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
        struct ov4689_dev *sensor = to_ov4689_dev(sd);
        int ret = 0;
 
@@ -2943,6 +2945,10 @@ static int ov4689_probe(struct i2c_client *client)
        if (IS_ERR(sensor->reset_gpio))
                return PTR_ERR(sensor->reset_gpio);
 
+       if (!sensor->reset_gpio) {
+               dev_err(dev, "--------Could not parse reset_gpio\n");
+       }
+
        v4l2_i2c_subdev_init(&sensor->sd, client, &ov4689_subdev_ops);
 
        sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_common.h b/drivers/media/platform/starfive/v4l2_driver/stf_common.h
index 8793f36..7b65144 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_common.h
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_common.h
@@ -176,8 +176,8 @@ static inline void reg_clr_highest_bit(void __iomem *base, u32 reg)
 
 static inline void print_reg(unsigned int module, void __iomem *base, u32 reg)
 {
-       //st_debug(module, "REG 0x%x = 0x%x\n",
-       //              base + reg, ioread32(base + reg));
+       st_debug(module, "REG 0x%x = 0x%x\n",
+                       base + reg, ioread32(base + reg));
 }
 
 #endif /* STF_COMMON_H */

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_csi.c b/drivers/media/platform/starfive/v4l2_driver/stf_csi.c
index 834b10c..ce565fa 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_csi.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_csi.c
@@ -50,6 +50,10 @@ int stf_csi_subdev_init(struct stfcamss *stfcamss, int id)
 
 static int csi_set_power(struct v4l2_subdev *sd, int on)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
+       struct stf_csi_dev *csi_dev = v4l2_get_subdevdata(sd);
+
+       csi_dev->hw_ops->csi_power_on(csi_dev, (u8)on);
        return 0;
 }
 
@@ -67,6 +71,7 @@ __csi_get_format(struct stf_csi_dev *csi_dev,
 
 static int csi_set_stream(struct v4l2_subdev *sd, int enable)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
        struct stf_csi_dev *csi_dev = v4l2_get_subdevdata(sd);
        struct stf_csi_dev *csi0_dev = &csi_dev->stfcamss->csi_dev[0];
        struct v4l2_mbus_framefmt *format;
@@ -96,7 +101,7 @@ static int csi_set_stream(struct v4l2_subdev *sd, int enable)
        mutex_lock(&csi_dev->stream_lock);
        if (enable) {
                if (csi_dev->stream_count == 0) {
-                       csi_dev->hw_ops->csi_config_set(csi_dev);
+                       //csi_dev->hw_ops->csi_config_set(csi_dev);
                        csi_dev->hw_ops->csi_clk_enable(csi_dev);
                        csi_dev->hw_ops->csi_set_format(csi_dev,
                                        format->height,

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_csi.h b/drivers/media/platform/starfive/v4l2_driver/stf_csi.h
index 6e94664..4c7af15 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_csi.h
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_csi.h
@@ -22,6 +22,7 @@ struct csi_format {
 struct stf_csi_dev;
 
 struct csi_hw_ops {
+       int (*csi_power_on)(struct stf_csi_dev *csi_dev, u8 on);
        int (*csi_clk_enable)(struct stf_csi_dev *csi_dev);
        int (*csi_clk_disable)(struct stf_csi_dev *csi_dev);
        int (*csi_config_set)(struct stf_csi_dev *csi_dev);

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c b/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c
index 1ac10a5..f7cc07a 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c
@@ -6,6 +6,8 @@
  *
  */
 #include "stfcamss.h"
+#include <linux/regmap.h>
+#include <soc/starfive/jh7110_pmic.h>
 
 #define CSI2RX_DEVICE_CFG_REG                  0x000
 
@@ -35,10 +37,37 @@
 #define CSI2RX_LANES_MAX       4
 #define CSI2RX_STREAMS_MAX     4
 
+static int stf_csi_power_on(struct stf_csi_dev *csi_dev, u8 on)
+{
+       printk("---------[%s, %d]", __func__, __LINE__);
+       struct stfcamss *stfcamss = csi_dev->stfcamss;
+       void __iomem *aon_syscon;
+
+       pmic_set_domain(POWER_SW_0_REG, POWER_SW_0_VDD18_MIPIRX, on);
+       pmic_set_domain(POWER_SW_0_REG, POWER_SW_0_VDD09_MIPIRX, on);
+
+       // regmap_update_bits(stfcamss->reg_aon_syscon,
+       //      stfcamss->aon_dphy_power,
+       //      AON_GP_REG_MASK,
+       //      0x80000000);
+
+       aon_syscon = ioremap(0x17010000, 0x1000);
+       reg_write(aon_syscon, 0x00, 0x80000000);
+
+       return 0;
+}
+
 static int stf_csi_clk_enable(struct stf_csi_dev *csi_dev)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
        struct stfcamss *stfcamss = csi_dev->stfcamss;
 
+       clk_set_rate(stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk, 204800000);
+       clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
+       clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
+       clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
+       clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
+
        reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
        reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
        reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
@@ -46,17 +75,12 @@ static int stf_csi_clk_enable(struct stf_csi_dev *csi_dev)
        reset_control_deassert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
        reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
 
-       clk_set_rate(stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk, 204800000);
-       clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF0].clk);
-       clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF1].clk);
-       clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF2].clk);
-       clk_prepare_enable(stfcamss->sys_clk[STFCLK_PIXEL_CLK_IF3].clk);
-
        return 0;
 }
 
 static int stf_csi_clk_disable(struct stf_csi_dev *csi_dev)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
        struct stfcamss *stfcamss = csi_dev->stfcamss;
 
        reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
@@ -140,15 +164,12 @@ static int stf_csi_set_format(struct stf_csi_dev *csi_dev,
                break;
        case SENSOR_ISP0:
                if (is_raw10)
-                       reg_set_bit(vin->sysctrl_base,
-                                       SYSCTRL_VIN_SRC_DW_SEL,
-                                       BIT(4), 1 << 4);
+                       reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
+                               BIT(12),
+                               1<<12);
                break;
        case SENSOR_ISP1:
-               if (is_raw10)
-                       reg_set_bit(vin->sysctrl_base,
-                                       SYSCTRL_VIN_SRC_DW_SEL,
-                                       BIT(5), 1 << 5);
+               st_err(ST_CSI, "please check csi_dev s_type:%d\n", csi_dev->s_type);
        default:
                break;
        }
@@ -168,6 +189,7 @@ static void csi2rx_reset(void *reg_base)
 
 static int csi2rx_start(struct stf_csi_dev *csi_dev, void *reg_base)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
        struct stfcamss *stfcamss = csi_dev->stfcamss;
        struct csi2phy_cfg *csiphy =
                stfcamss->csiphy_dev[csi_dev->csiphy_id].csiphy;
@@ -179,24 +201,14 @@ static int csi2rx_start(struct stf_csi_dev *csi_dev, void *reg_base)
                st_err(ST_CSI, "csiphy%d sensor not exist use csiphy%d init.\n",
                                csi_dev->csiphy_id, !csi_dev->csiphy_id);
                csiphy = stfcamss->csiphy_dev[!csi_dev->csiphy_id].csiphy;
-               if (!csiphy) {
-                       st_err(ST_CSI, "csiphy%d sensor not exist\n",
-                               !csi_dev->csiphy_id);
-                       return -EINVAL;
-               }
        }
 
        csi2rx_reset(reg_base);
 
        reg = csiphy->num_data_lanes << 8;
        for (i = 0; i < csiphy->num_data_lanes; i++) {
-#ifndef USE_CSIDPHY_ONE_CLK_MODE
                reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csiphy->data_lanes[i]);
                set_bit(csiphy->data_lanes[i] - 1, &lanes_used);
-#else
-               reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, i + 1);
-               set_bit(i, &lanes_used);
-#endif
        }
 
        /*
@@ -214,20 +226,22 @@ static int csi2rx_start(struct stf_csi_dev *csi_dev, void *reg_base)
        }
 
        writel(reg, reg_base + CSI2RX_STATIC_CFG_REG);
+       printk("---------[%s, %d] CSI2RX_STATIC_CFG_REG= %d", __func__, __LINE__, reg);
 
        // 0x40 DPHY_LANE_CONTROL
        reg = 0;
-#ifndef USE_CSIDPHY_ONE_CLK_MODE
-       for (i = 0; i < csiphy->num_data_lanes; i++)
-               reg |= 1 << (csiphy->data_lanes[i] - 1)
-                       | 1 << (csiphy->data_lanes[i] + 11);
-#else
+// #ifndef USE_CSIDPHY_ONE_CLK_MODE
+//     for (i = 0; i < csiphy->num_data_lanes; i++)
+//             reg |= 1 << (csiphy->data_lanes[i] - 1)
+//                     | 1 << (csiphy->data_lanes[i] + 11);
+// #else
        for (i = 0; i < csiphy->num_data_lanes; i++)
                reg |= 1 << i | 1 << (i + 12);
-#endif
+// #endif
 
        reg |= 1 << 4 | 1 << 16;
        writel(reg, reg_base + CSI2RX_DPHY_LANE_CONTROL);
+       printk("---------[%s, %d] CSI2RX_DPHY_LANE_CONTROL= %d", __func__, __LINE__, reg);
 
        /*
         * Create a static mapping between the CSI virtual channels
@@ -264,6 +278,7 @@ static void csi2rx_stop(struct stf_csi_dev *csi_dev, void *reg_base)
 
 static int stf_csi_stream_set(struct stf_csi_dev *csi_dev, int on)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
        struct stfcamss *stfcamss = csi_dev->stfcamss;
        struct stf_vin_dev *vin = csi_dev->stfcamss->vin;
        void *reg_base = NULL;
@@ -279,6 +294,19 @@ static int stf_csi_stream_set(struct stf_csi_dev *csi_dev, int on)
        case SENSOR_VIN:
                clk_set_parent(stfcamss->sys_clk[STFCLK_AXIWR].clk,
                        stfcamss->sys_clk[STFCLK_MIPI_RX0_PXL].clk);
+
+               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20,
+                       BIT(3)|BIT(2)|BIT(1)|BIT(0),
+                       0<<0);          //u0_vin_cnfg_axiwr0_channel_sel
+               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
+                       BIT(14)|BIT(13),
+                       1<<13);
+               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
+                       BIT(16)|BIT(15),
+                       0<<15);
+               reg_set_bit(vin->sysctrl_base, SYSCONSAIF_SYSCFG_28,
+                       BIT(12)|BIT(11)|BIT(10)|BIT(9)|BIT(8)|BIT(7)|BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2),
+                       1920 / 4 - 1);
                break;
        case SENSOR_ISP0:
                clk_set_parent(stfcamss->sys_clk[STFCLK_WRAPPER_CLK_C].clk,
@@ -286,15 +314,16 @@ static int stf_csi_stream_set(struct stf_csi_dev *csi_dev, int on)
 
                reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
                        BIT(7)|BIT(6),
-                       0<<6);
+                       0<<6);          //u0_vin_cnfg_mipi_byte_en_isp0
                reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
                        BIT(11)|BIT(10)|BIT(9)|BIT(8),
-                       0<<8);
+                       0<<8);          //u0_vin_cnfg_mipi_channel_sel0
                reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
-                       BIT(12), 0<<12);
+                       BIT(12),
+                       1<<12);         //u0_vin_cnfg_p_i_mipi_header_en0
                reg_set_bit(vin->sysctrl_base,  SYSCONSAIF_SYSCFG_36,
                        BIT(16)|BIT(15)|BIT(14)|BIT(13),
-                       0<<13);
+                       0<<13);         //u0_vin_cnfg_pix_num
                break;
        case SENSOR_ISP1:
                st_err(ST_CSI, "please check csi_dev s_type:%d\n", csi_dev->s_type);
@@ -326,6 +355,7 @@ void dump_csi_reg(void *__iomem csibase, int id)
 }
 
 struct csi_hw_ops csi_ops = {
+       .csi_power_on          = stf_csi_power_on,
        .csi_clk_enable        = stf_csi_clk_enable,
        .csi_clk_disable       = stf_csi_clk_disable,
        .csi_config_set        = stf_csi_config_set,

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_csiphy.c b/drivers/media/platform/starfive/v4l2_driver/stf_csiphy.c
index 0f36b9f..849fd42 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_csiphy.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_csiphy.c
@@ -37,6 +37,7 @@ int stf_csiphy_subdev_init(struct stfcamss *stfcamss, int id)
 
 static int csiphy_set_power(struct v4l2_subdev *sd, int on)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
 #ifdef CONFIG_VIDEO_CADENCE_CSI2RX
        struct stf_csiphy_dev *csiphy_dev = v4l2_get_subdevdata(sd);
 
@@ -48,6 +49,7 @@ static int csiphy_set_power(struct v4l2_subdev *sd, int on)
 
 static int csiphy_set_stream(struct v4l2_subdev *sd, int enable)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
        struct stf_csiphy_dev *csiphy_dev = v4l2_get_subdevdata(sd);
 
        mutex_lock(&csiphy_dev->stream_lock);
@@ -258,6 +260,7 @@ static int csiphy_link_setup(struct media_entity *entity,
                        const struct media_pad *local,
                        const struct media_pad *remote, u32 flags)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
        if ((local->flags & MEDIA_PAD_FL_SOURCE) &&
                (flags & MEDIA_LNK_FL_ENABLED)) {
                struct v4l2_subdev *sd;

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_csiphy_hw_ops.c b/drivers/media/platform/starfive/v4l2_driver/stf_csiphy_hw_ops.c
index 0577743..d26e416 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_csiphy_hw_ops.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_csiphy_hw_ops.c
@@ -7,6 +7,7 @@
 
 static int stf_csiphy_clk_set(struct stf_csiphy_dev *csiphy_dev, int on)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
        struct stfcamss *stfcamss = csiphy_dev->stfcamss;
        struct stf_vin_dev *vin = csiphy_dev->stfcamss->vin;
        static int init_flag;
@@ -140,8 +141,8 @@ int try_cfg(struct csi2phy_cfg2 *cfg, struct csi2phy_cfg *cfg0,
 static int csi2rx_dphy_config(struct stf_vin_dev *vin,
                struct stf_csiphy_dev *csiphy_dev)
 {
-       struct csi2phy_cfg2 cfg2 = {0};
-       struct csi2phy_cfg2 *cfg = &cfg2;
+       printk("---------[%s, %d]", __func__, __LINE__);
+       struct csi2phy_cfg *cfg;
        struct stf_csiphy_dev *csiphy0_dev =
                &csiphy_dev->stfcamss->csiphy_dev[0];
        struct stf_csiphy_dev *csiphy1_dev =
@@ -150,63 +151,128 @@ static int csi2rx_dphy_config(struct stf_vin_dev *vin,
        struct csi2phy_cfg *phy1cfg = csiphy1_dev->csiphy;
        int id = csiphy_dev->id;
 
-       if (!phy0cfg && !phy1cfg)
+       if (!phy0cfg)
                return -EINVAL;
 
-#ifdef USE_CSIDPHY_ONE_CLK_MODE
        if (id == 0) {
-               phy0cfg = csiphy0_dev->csiphy;
-               phy1cfg = NULL;
-       } else {
-               phy0cfg = NULL;
-               phy1cfg = csiphy1_dev->csiphy;
+               cfg = phy0cfg;
        }
-#endif
 
-       if (try_cfg(cfg, phy0cfg, phy1cfg))
-               return -EINVAL;
+       // if (try_cfg(cfg, phy0cfg, phy1cfg))
+       //      return -EINVAL;
+
+printk("---------[%s, %d]", __func__, __LINE__);
+
+       printk("---------[%s, %d] cfg->clock_lane0 = %d\n",
+               __func__, __LINE__, cfg->clock_lane);
+       // printk("---------[%s, %d] cfg->clock_lane1 =s %d\n",
+       //      __func__, __LINE__, cfg->clock1_lane);
+       printk("---------[%s, %d] cfg->data_lanes[0] = %d\n",
+               __func__, __LINE__, cfg->data_lanes[0]);
+       printk("---------[%s, %d] cfg->data_lanes[1] = %d\n",
+               __func__, __LINE__, cfg->data_lanes[1]);
+       printk("---------[%s, %d] cfg->data_lanes[2] = %d\n",
+               __func__, __LINE__, cfg->data_lanes[2]);
+       printk("---------[%s, %d] cfg->data_lanes[3] = %d\n",
+               __func__, __LINE__, cfg->data_lanes[3]);
+
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_4, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_8, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_12, 0xff0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_16, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_20, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_24, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_28, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_32, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_36, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_40, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_44, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_48, 0x24000000);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_52, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_56, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_60, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_64, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_68, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_72, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_76, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_80, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_84, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_88, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_92, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_96, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_100, 0x02000000);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_104, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_108, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_112, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_116, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_120, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_124, 0xc);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_128, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_132, 0xcc500000);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_136, 0xcc);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_140, 0x0);
+       reg_write(vin->rstgen_base, M31DPHY_APBCFGSAIF__SYSCFG_144, 0x0);
+
+       reg_set_bit(vin->rstgen_base,           //r100_ctrl0_2d1c_efuse_en
+               M31DPHY_APBCFGSAIF__SYSCFG_0,
+               BIT(6), 1<<6);
+       reg_set_bit(vin->rstgen_base,           //r100_ctrl0_2d1c_efuse_in
+               M31DPHY_APBCFGSAIF__SYSCFG_0,
+               BIT(12)|BIT(11)|BIT(10)|BIT(9)|BIT(8)|BIT(7), 0x1b<<7);
+       reg_set_bit(vin->rstgen_base,           //r100_ctrl1_2d1c_efuse_en
+               M31DPHY_APBCFGSAIF__SYSCFG_0,
+               BIT(13), 1<<13);
+       reg_set_bit(vin->rstgen_base,           //r100_ctrl1_2d1c_efuse_in
+               M31DPHY_APBCFGSAIF__SYSCFG_0,
+               BIT(19)|BIT(18)|BIT(17)|BIT(16)|BIT(15)|BIT(14), 0x1b<<14);
+
+       reg_set_bit(vin->rstgen_base,           //data_bus16_8
+               M31DPHY_APBCFGSAIF__SYSCFG_184,
+               BIT(8), 0<<8);
 
-       id = cfg->num_clks == 2 ? 1 : 0;
+       reg_set_bit(vin->rstgen_base,           //debug_mode_sel
+               M31DPHY_APBCFGSAIF__SYSCFG_184,
+               BIT(15)|BIT(14)|BIT(13)|BIT(12)|BIT(11)|BIT(10)|BIT(9), 0x5a<<9);
 
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,                   //dpdn_swap_clk0
                M31DPHY_APBCFGSAIF__SYSCFG_188,
                BIT(0), 0<<0);
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,                   //dpdn_swap_clk1
                M31DPHY_APBCFGSAIF__SYSCFG_188,
                BIT(1), 0<<1);
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,                   //dpdn_swap_lan0
                M31DPHY_APBCFGSAIF__SYSCFG_188,
                BIT(2), 0<<2);
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,                   //dpdn_swap_lan1
                M31DPHY_APBCFGSAIF__SYSCFG_188,
                BIT(3), 0<<3);
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,                   //dpdn_swap_lan2
                M31DPHY_APBCFGSAIF__SYSCFG_188,
                BIT(4), 0<<4);
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,                   //dpdn_swap_lan3
                M31DPHY_APBCFGSAIF__SYSCFG_188,
                BIT(5), 0<<5);
 
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,                   //endable lan0
                M31DPHY_APBCFGSAIF__SYSCFG_188,
                BIT(8), 1<<8);
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,                   //endable lan1
                M31DPHY_APBCFGSAIF__SYSCFG_188,
                BIT(9), 1<<9);
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,                   //endable lan2
                M31DPHY_APBCFGSAIF__SYSCFG_188,
                BIT(10), 1<<10);
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,                   //endable lan3
                M31DPHY_APBCFGSAIF__SYSCFG_188,
                BIT(11), 1<<11);
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,                   //gpi_en
                M31DPHY_APBCFGSAIF__SYSCFG_188,
                BIT(17)|BIT(16)|BIT(15)|BIT(14)|BIT(13)|BIT(12),
                0<<12);
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,                   //hs_freq_change_clk0
                M31DPHY_APBCFGSAIF__SYSCFG_188,
                BIT(18), 0<<18);
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,                   //hs_freq_change_clk1
                M31DPHY_APBCFGSAIF__SYSCFG_188,
                BIT(19), 0<<19);
 
@@ -215,7 +281,7 @@ static int csi2rx_dphy_config(struct stf_vin_dev *vin,
                BIT(22)|BIT(21)|BIT(20), cfg->clock_lane<<20);          //clock lane 0
        reg_set_bit(vin->rstgen_base,
                M31DPHY_APBCFGSAIF__SYSCFG_188,
-               BIT(25)|BIT(24)|BIT(23), cfg->clock1_lane<<23);         //clock lane 1
+               BIT(25)|BIT(24)|BIT(23), 5<<23);         //clock lane 1
 
        reg_set_bit(vin->rstgen_base,
                M31DPHY_APBCFGSAIF__SYSCFG_188,
@@ -230,16 +296,47 @@ static int csi2rx_dphy_config(struct stf_vin_dev *vin,
                M31DPHY_APBCFGSAIF__SYSCFG_192,
                BIT(5)|BIT(4)|BIT(3), cfg->data_lanes[3]<<3);           //data lane 3
 
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,           //mp_test_en
                M31DPHY_APBCFGSAIF__SYSCFG_192,
                BIT(6), 0<<6);
-       reg_set_bit(vin->rstgen_base,
+       reg_set_bit(vin->rstgen_base,           //mp_test_mode_sel
                M31DPHY_APBCFGSAIF__SYSCFG_192,
                BIT(11)|BIT(10)|BIT(9)|BIT(8)|BIT(7), 0<<7);
-       reg_set_bit(vin->rstgen_base,
+
+       reg_set_bit(vin->rstgen_base,           //pll_clk_sel
+               M31DPHY_APBCFGSAIF__SYSCFG_192,
+               BIT(20)|BIT(19)|BIT(18)|BIT(17)|BIT(16)|BIT(15)|BIT(14)|BIT(13)|BIT(12),
+               0x37c<<12);
+
+       reg_set_bit(vin->rstgen_base,           //rx_1c2c_sel
                M31DPHY_APBCFGSAIF__SYSCFG_200,
                BIT(8), 0<<8);
 
+       reg_set_bit(vin->rstgen_base,           //precounter in clk0
+               M31DPHY_APBCFGSAIF__SYSCFG_192,
+               BIT(29)|BIT(28)|BIT(27)|BIT(26)|BIT(25)|BIT(24)|BIT(23)|BIT(22),
+               8<<22);
+       reg_set_bit(vin->rstgen_base,           //precounter in clk1
+               M31DPHY_APBCFGSAIF__SYSCFG_196,
+               BIT(7)|BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0),
+               8<<0);
+       reg_set_bit(vin->rstgen_base,           //precounter in lan0
+               M31DPHY_APBCFGSAIF__SYSCFG_196,
+               BIT(15)|BIT(14)|BIT(13)|BIT(12)|BIT(11)|BIT(10)|BIT(9)|BIT(8),
+               7<<8);
+       reg_set_bit(vin->rstgen_base,           //precounter in lan1
+               M31DPHY_APBCFGSAIF__SYSCFG_196,
+               BIT(23)|BIT(22)|BIT(21)|BIT(20)|BIT(19)|BIT(18)|BIT(17)|BIT(16),
+               7<<16);
+       reg_set_bit(vin->rstgen_base,           //precounter in lan2
+               M31DPHY_APBCFGSAIF__SYSCFG_196,
+               BIT(31)|BIT(30)|BIT(29)|BIT(28)|BIT(27)|BIT(26)|BIT(25)|BIT(24),
+               7<<24);
+       reg_set_bit(vin->rstgen_base,           //precounter in lan3
+               M31DPHY_APBCFGSAIF__SYSCFG_200,
+               BIT(7)|BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0),
+               7<<0);
+
        return 0;
 }
 

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_isp_hw_ops.c b/drivers/media/platform/starfive/v4l2_driver/stf_isp_hw_ops.c
index ea4e6ce..e8e3876 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_isp_hw_ops.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_isp_hw_ops.c
@@ -311,9 +311,9 @@ static int stf_isp_set_format(struct stf_isp_dev *isp_dev,
 
        if (isp_dev->id == 0) {
                ispbase = vin->isp_isp0_base;
-               isp_settings = isp_sc2235_settings;
+               //isp_settings = isp_sc2235_settings;
                //isp_settings = isp_ov13850_settings;
-               //isp_settings = isp_1920_1080_settings;
+               isp_settings = isp_1920_1080_settings;
        } else {
                ispbase = vin->isp_isp1_base;
                isp_settings = isp_sc2235_settings;

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_vin.c b/drivers/media/platform/starfive/v4l2_driver/stf_vin.c
index d08effd..4314cbe 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_vin.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_vin.c
@@ -153,6 +153,7 @@ out:
 
 static int vin_set_power(struct v4l2_subdev *sd, int on)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
        struct vin_line *line = v4l2_get_subdevdata(sd);
        struct stf_vin2_dev *vin_dev = line_to_vin2_dev(line);
 
@@ -259,6 +260,7 @@ static int vin_disable_output(struct vin_line *line)
 
 static int vin_set_stream(struct v4l2_subdev *sd, int enable)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
        struct vin_line *line = v4l2_get_subdevdata(sd);
        struct stf_vin2_dev *vin_dev = line_to_vin2_dev(line);
 

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c b/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c
index 1277726..0f742d2 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c
@@ -106,6 +106,7 @@ static int stf_vin_config_set(struct stf_vin2_dev *vin_dev)
 
 static int stf_vin_wr_stream_set(struct stf_vin2_dev *vin_dev, int on)
 {
+       printk("---------[%s, %d]", __func__, __LINE__);
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
        struct stfcamss *stfcamss = vin_dev->stfcamss;
 
@@ -113,8 +114,6 @@ static int stf_vin_wr_stream_set(struct stf_vin2_dev *vin_dev, int on)
        if (on) {
                reg_set(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20, U0_VIN_CNFG_AXIWR0_EN);
        } else {
-               reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
-               usleep_range(500, 1000);
                reg_clear(vin->sysctrl_base, SYSCONSAIF_SYSCFG_20, U0_VIN_CNFG_AXIWR0_EN);
        }
        print_reg(ST_VIN, vin->sysctrl_base, SYSCONSAIF_SYSCFG_20);
@@ -220,19 +219,6 @@ void dump_vin_reg(void *__iomem regbase)
        print_reg(ST_VIN, regbase, 0x20);
        print_reg(ST_VIN, regbase, 0x24);
        print_reg(ST_VIN, regbase, 0x28);
-       print_reg(ST_VIN, regbase, 0x2c);
-       print_reg(ST_VIN, regbase, 0x30);
-       print_reg(ST_VIN, regbase, 0x34);
-       print_reg(ST_VIN, regbase, 0x38);
-       print_reg(ST_VIN, regbase, 0x3c);
-       print_reg(ST_VIN, regbase, 0x40);
-       print_reg(ST_VIN, regbase, 0x44);
-       print_reg(ST_VIN, regbase, 0x48);
-       print_reg(ST_VIN, regbase, 0x4c);
-       print_reg(ST_VIN, regbase, 0x50);
-       print_reg(ST_VIN, regbase, 0x54);
-       print_reg(ST_VIN, regbase, 0x58);
-       print_reg(ST_VIN, regbase, 0x5c);
 }
 
 struct vin_hw_ops vin_ops = {