dt-bindings: reset: a10sr: Add Arria10 SR Reset Controller offsets
authorThor Thayer <thor.thayer@linux.intel.com>
Wed, 22 Feb 2017 17:10:16 +0000 (11:10 -0600)
committerPhilipp Zabel <p.zabel@pengutronix.de>
Wed, 15 Mar 2017 11:19:10 +0000 (12:19 +0100)
The Arria10 System Resource Chip reset controller handles the
Arria10 peripheral PHYs. This patch adds the offsets for
these PHYs.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
MAINTAINERS
include/dt-bindings/reset/altr,rst-mgr-a10sr.h [new file with mode: 0644]

index c265a5f..27558d5 100644 (file)
@@ -654,6 +654,7 @@ S:  Maintained
 F:     drivers/gpio/gpio-altera-a10sr.c
 F:     drivers/mfd/altera-a10sr.c
 F:     include/linux/mfd/altera-a10sr.h
+F:     include/dt-bindings/reset/altr,rst-mgr-a10sr.h
 
 ALTERA TRIPLE SPEED ETHERNET DRIVER
 M:     Vince Bridgers <vbridger@opensource.altera.com>
diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10sr.h b/include/dt-bindings/reset/altr,rst-mgr-a10sr.h
new file mode 100644 (file)
index 0000000..9855925
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ *  Copyright Intel Corporation (C) 2017. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip
+ *
+ * Adapted from altr,rst-mgr-a10.h
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H
+
+/* Peripheral PHY resets */
+#define A10SR_RESET_ENET_HPS   0
+#define A10SR_RESET_PCIE       1
+#define A10SR_RESET_FILE       2
+#define A10SR_RESET_BQSPI      3
+#define A10SR_RESET_USB                4
+
+#define A10SR_RESET_NUM                5
+
+#endif