Move SDD document into contrib/nnc (#1641)

This commit moves SDD document from nncc/doc in md formant into nncc/contrib/nnc in rst format

Signed-off-by: Roman Rusyaev <r.rusyaev@samsung.com>

diff --git a/contrib/nnc/doc/project/18_NN_Compiler_and_Optimizer_SDD.rst b/contrib/nnc/doc/project/18_NN_Compiler_and_Optimizer_SDD.rst
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+=======================
+SW Development Document
+=======================
+
+.. contents::
+
+.. section-numbering::
+
+.. raw:: pdf
+
+   PageBreak oneColumn
+
+
+**Revision history**
+
++-------+-------------+-----------------------------+--------------------------+---------------------+
+| Ver.  | Date        | Contents                    | Author                   | Approver            |
++=======+=============+=============================+==========================+=====================+
+| 0.1   | 2018.04.12  | Initial version             | Vostokov Sergey          | Sung-Jae Lee        |
++-------+-------------+-----------------------------+--------------------------+---------------------+
+| 0.2   | 2018.04.16  | SE member in-charge review  | Ilya Lopatin             |                     |
++-------+-------------+-----------------------------+--------------------------+---------------------+
+| 1.0   | 2018.04.17  | Final Execution DR version  | Vostokov Sergey          | Sung-Jae Lee        |
++-------+-------------+-----------------------------+--------------------------+---------------------+
+| 1.1   | 2018.04.17  | Add SW Quality Verification | Vostokov Sergey          | Sung-Jae Lee        |
++-------+-------------+-----------------------------+--------------------------+---------------------+
+
+.. include:: project_terms_and_abbreviation.rst
+
+Project Overview
+================
+
+Purpose and Scope
+-----------------
+
+
+.. include:: project_purpose_and_scope.rst
+.. include:: project_target_model.rst
+
+Assumptions, Dependencies and Constraints
+-----------------------------------------
+
+.. include:: project_sw_hw_constraints.rst
+
+Development Plan And Result
+===========================
+
+Development Schedule
+--------------------
+
+|
+ **Table 2-1. SW Development Schedule**
+|
+
++-------------------+----------------------------+------------+------------+--------------+------------+--------------------+
+| Task              | Deliverable                | Plan start | Plan end   | Result start | Result end | Responsibility     |
++===================+============================+============+============+==============+============+====================+
+| Prepare SW        | SRS                        | 04.2018    | 04.2018    |  04.2018     | 04.2018    | S\. Vostokov       |
+| requirements      |                            |            |            |              |            |                    |
++-------------------+----------------------------+------------+------------+--------------+------------+--------------------+
+| Prepare initial   | STD                        | 04.2018    | 04.2018    |  04.2018     | 04.2018    | S\. Vostokov       |
+| SW Test Document  |                            |            |            |              |            |                    |
++-------------------+----------------------------+------------+------------+--------------+------------+--------------------+
+| Prepare Initial   | SDD                        | 04.2018    | 04.2018    |  04.2018     | 04.2018    | S\. Vostokov       |
+| Project Plan      |                            |            |            |              |            |                    |
++-------------------+----------------------------+------------+------------+--------------+------------+--------------------+
+| Prepare           | STD                        | 04.2018    | 06.2018    |  04.2018     | 06.2018    | S\. Vostokov       |
+| SW Test Document  |                            |            |            |              |            |                    |
++-------------------+----------------------------+------------+------------+--------------+------------+--------------------+
+| Prepare design    | HLD, DLD                   | 05.2018    | 08.2018    |  05.2018     | 08.2018    | S\. Vostokov       |
+| document          |                            |            |            |              |            |                    |
++-------------------+----------------------------+------------+------------+--------------+------------+--------------------+
+| Prepare test      | STD, UTR                   | 04.2018    | 10.2018    |              |            | S\. Vostokov       |
+| result            |                            |            |            |              |            |                    |
++-------------------+----------------------------+------------+------------+--------------+------------+--------------------+
+| Prepare project   | SDD,                       | 05.2018    | 12.2018    |              |            | S\. Vostokov       |
+| completion        | Project completion report  |            |            |              |            |                    |
+| documents         |                            |            |            |              |            |                    |
++-------------------+----------------------------+------------+------------+--------------+------------+--------------------+
+| Implement Caffe   | Caffe NN model Importer    | 05.2018    | 09.2018    | 05.2018      | 09.2018    | S\. Vostokov       |
+| Importer          |                            |            |            |              |            |                    |
++-------------------+----------------------------+------------+------------+--------------+------------+--------------------+
+| Implement code    | Code emitter               | 05.2018    | 09.2018    | 05.2018      | 09.2018    | S\. Vostokov       |
+| emitter for CPU   |                            |            |            |              |            |                    |
++-------------------+----------------------------+------------+------------+--------------+------------+--------------------+
+| Implement TF Lite | TensorFlow Lite NN model   | 05.2018    | 11.2018    |              |            | S\. Vostokov       |
+| Importer          | Importer                   |            |            |              |            |                    |
++-------------------+----------------------------+------------+------------+--------------+------------+--------------------+
+| Implement code    | Code emitter               | 02.2018    | 11.2018    |              |            | S\. Vostokov       |
+| emitter for GPU   |                            |            |            |              |            |                    |
++-------------------+----------------------------+------------+------------+--------------+------------+--------------------+
+
+
+SW Metrics
+----------
+
+.. list-table:: Table 2-2. SW Metrics
+   :widths: 5 10 5 7 5 4 8
+   :header-rows: 1
+
+   * - Category
+     - Metric
+     - Collection Method
+     - Collection Period
+     - Planned
+     - Actual
+     - Responsibility
+
+   * - Quality
+     - Test pass rate
+     - GTest
+     - 22.02.2018 - 31.12.2018
+     - 100%
+     -
+     - S\. Vostokov
+
+   * - Quality
+     - Defects density
+     - Defect management system
+     - 22.02.2018 - 31.12.2018
+     - <= 1 defect/KLOC
+     -
+     - S\. Vostokov
+
+   * - Quality
+     - Defects removal rate
+     - Defect management system
+     - 22.02.2018 - 31.12.2018
+     - 100%
+     -
+     - S\. Vostokov
+
+   * - Quality
+     - Critical defects
+     - Static analysis
+     - 22.02.2018 - 31.12.2018
+     - 0
+     -
+     - S\. Vostokov
+
+   * - Quality
+     - Major defects
+     - Static analysis
+     - 22.02.2018 - 31.12.2018
+     - 0
+     -
+     - S\. Vostokov
+
+   * - Quality
+     - Code review issue removal
+     - Samsung Research github
+     - 22.02.2018 - 31.12.2018
+     - 100%
+     -
+     - S\. Vostokov
+
+   * - Quality
+     - Comments Rate
+     - ``cloc`` tool
+     - 22.02.2018 - 31.12.2018
+     - Exceed 20%
+     -
+     - S\. Vostokov
+
+   * - Quality
+     - Cyclomatic Complexity
+     - SVACE
+     - 22.02.2018 - 31.12.2018
+     - < 50
+     -
+     - S\. Vostokov
+
+   * - Quality
+     - Unused Items (Unused Files, Unused Functions, Unused Global Variables)
+     - gcc/g++
+     - 22.02.2018 - 31.12.2018
+     - 0
+     -
+     - S\. Vostokov
+
+   * - Process
+     - Project On-time Completion Rate
+     - PLM
+     - 22.02.2018 - 31.12.2018
+     - 100%
+     -
+     - S\. Vostokov
+
+   * - Process
+     - Milestone On-time Completion Rate
+     - PLM
+     - 22.02.2018 - 31.12.2018
+     - 100%
+     -
+     - S\. Vostokov
+
+   * - Process
+     - Process compliance
+     - Audit
+     - 22.02.2018 - 31.12.2018
+     - 100%
+     -
+     - S\. Vostokov
+
+
+SW Configurations Management
+----------------------------
+
+Document
+````````
+
+
+.. list-table:: Table 2-3. Document Configuration Item
+   :widths: 2 20 5 8
+   :header-rows: 1
+
+   * - No
+     - Configuration Item
+     - Location
+     - Submitter
+
+   * - 1
+     - SW Requirement Specification
+     - PLM
+     - S\. Vostokov
+
+   * - 2
+     - SW Development Document
+     - PLM
+     - S\. Vostokov
+
+   * - 3
+     - SW High Level Document
+     - PLM
+     - S\. Vostokov
+
+
+   * - 4
+     - SW Detailed Level Document
+     - PLM
+     - S\. Vostokov
+
+   * - 5
+     - SW System Test Document
+     - PLM
+     - S\. Vostokov
+
+   * - 6
+     - SW Unit Test Report
+     - PLM
+     - S\. Vostokov
+
+
+SW Source Code
+``````````````
+
+
+SW Repository: https://github.sec.samsung.net/STAR/nncc
+
+::
+
+  git clone https://github.sec.samsung.net/STAR/nncc.git
+
+
+
+Baseline
+````````
+
+.. list-table:: Table 2-4. Baseline Establishment
+   :widths: 5 5 8
+   :header-rows: 1
+
+   * - Phase
+     - Baseline Name
+     - SW Configuration Item
+
+   * - 04.2018 Plan
+     - Execution DR
+     - SW Requirement Specification, SW Development Document, System Test Document initial version
+
+   * - 06.2018 Execution
+     - DR1
+     - System Test Document
+
+   * - 08.2018 Execution
+     - Design document
+     - SW High Level Document, SW Detailed Design Document
+
+   * - 09.2018 Execution
+     - DR2
+     -
+
+   * - 10.2018 Execution
+     - Test report
+     - SW System Test Document (result), SW Unit Test Report
+
+   * - 12.2018 Completion
+     - Project Completion
+     - Project Completion Report
+
+SW Quality Verification
+=======================
+
+SW Verification
+---------------
+
+
+.. list-table:: Table 3-1. SW Verification Plan and Result
+   :widths: 4 11 11 8 8 10 7 6
+   :header-rows: 1
+
+   * - No
+     - Verification Item
+     - Quality Goal
+     - Tool
+     - Phase
+     - Development Team Member in Charge
+     - Result
+     - Note
+
+   * - 1
+     - Open source License Verification
+     - Clear violations of open source obligation
+     - ProtexIP
+     - Execution
+     - Vostokov Sergey
+     -
+     -
+
+   * - 2
+     - Potential Defect
+     - Fix all defects
+     - Svace
+     - Test
+     - Vostokov Sergey
+     -
+     -
+
+   * - 3
+     - System Defect
+     - Fix Critical/ Major defects
+     - Github
+     - Test
+     - Vostokov Sergey
+     -
+     -
+
+Static Analysis
+---------------
+
+.. list-table:: Table 3-3. Static Analysis Verification
+   :widths: 5 20 10 7 20
+   :header-rows: 1
+
+   * - No
+     - Activity
+     - Schedule
+     - Result
+     - Comment
+
+   * - 1
+     - SA Verification I (SVACE)
+     - 28.09.2018
+     -
+     -
+
+   * - 2
+     - SA Verification II (SVACE)
+     - 30.11.2018
+     -
+     -
+
+   * - 2
+     - SA Verification III (SVACE)
+     - 31.12.2018
+     -
+     -
+
+Coding Standard
+---------------
+
+.. list-table:: Table 3-4. Coding Standard Verification
+   :widths: 5 20 10 7 20
+   :header-rows: 1
+
+   * - No
+     - Activity
+     - Schedule
+     - Result
+     - Comment
+
+   * - 1
+     - Coding standard enforcement with ``clang-format`` tool.
+     - Regular
+     -
+     -
+
+
+Convergence (integration testing)
+---------------------------------
+
+Out of scope since the integration with other SW is not required by SW Requirement Specification.
+
+Dynamic Analysis
+----------------
+
+
+.. list-table:: Table 3-5. Dynamic Analysis Verification
+   :widths: 5 20 10 7 20
+   :header-rows: 1
+
+   * - No
+     - Activity
+     - Schedule
+     - Result
+     - Comment
+
+   * - 1
+     - DA Verification I
+     - 28.09.2018
+     -
+     -
+
+   * - 2
+     - DA Verification II
+     - 30.11.2018
+     -
+     -
+
+   * - 2
+     - DA Verification III
+     - 31.12.2018
+     -
+     -
+
+Architecture Analysis
+---------------------
+
+SW architecture verification is managed by HQ.
+
+
+SW Security
+-----------
+
+Out of the project scope since the project is not related to SW security.
+
+
+Code Review
+-----------
+
+
+.. list-table::
+   :widths: 5 20 10 7 20
+   :header-rows: 1
+
+   * - No
+     - Activity
+     - Schedule
+     - Result
+     - Comment
+
+   * - 1
+     - Code review
+     - Regular
+     -
+     - All code is reviewed manually using ``github`` tool before committing
+
+Risk Management
+===============
+
+
+.. list-table:: Table 4-1. SW Risk Management
+   :widths: 7 12 12 10 12 12
+   :header-rows: 1
+
+   * - Priority
+     - Risk Description
+     - Risk Reduction Solution
+     - Schedule
+     - Result
+     - Responsibility
+
+   * - 1
+     - Project scope is changed due extra HQ request
+     - Discuss the new requirements via email and messenger, update SRS
+     - 02.2018 - 12.2018
+     -
+     - S\. Vostokov
+
+   * - 2
+     - Unavoidable technical difficulties during requirements implementation
+     - Submit requirements changes and get confirmation from HQ
+     - 02.2018 - 12.2018
+     -
+     - S\. Vostokov
+
+   * - 3
+     - Not enough HR
+     - Hire team members as soon as possible, request assistance from other teams
+     - 02.2018 - 12.2018
+     -
+     - S\. Vostokov
+
+   * - 4
+     - Use of GPL code
+     - Minimize usage of GPL code, wrap GPL modules with well-defined interfaces
+       so they can be easily replaced.
+     - 02.2018 - 12.2018
+     -
+     - S\. Vostokov
+
+   * - 5
+     - Requirements would change due external or internal circumstances, e.g. new technology or product launch
+     - Discuss project changes and make corrections
+     - 02.2018 - 12.2018
+     -
+     - S\. Vostokov
+
+
+**References**
+
+Competitors:
+
+.. [#] `NNVM: Open Compiler for AI Frameworks <https://github.com/dmlc/nnvm>`_.
+.. [#] `Latte.jl: A high-performance DSL for deep neural networks in Julia <https://github.com/IntelLabs/Latte.jl>`_.
+.. [#] `DNNDK: Full-stack solution for deep learning development & deployment <http://www.deephi.com/dnndk.html>`_.
+.. [#] `nngraph: Neural Network Graph Package <https://github.com/torch/nngraph>`_.
+.. [#] `Richard Wei, Lane Schwartz, Vikram Adve, DLVM: A modern compiler infrastructure for deep learning systems, arXiv:1711.03016, 2017 <http://dlvm.org/>`_.
+.. [#] `XLA (Accelerated Linear Algebra): a domain-specific compiler for linear algebra that optimizes TensorFlow computations <https://www.tensorflow.org/performance/xla>`_.
+.. [#] `nGraph: an open source C++ library, compiler and runtime for Deep Learning frameworks <https://github.com/NervanaSystems/ngraph>`_.