+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -loop-unroll -verify-loop-lcssa -S < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@b = external local_unnamed_addr global i32, align 4
-; CHECK-LABEL: @main
-; CHECK: exit.loopexit:
-; CHECK: {{.*}} = phi i32 [ %d.0, %h3 ]
-; CHECK: br label %exit
-; CHECK: exit.loopexit1:
-; CHECK: {{.*}} = phi i32 [ %d.0, %h3.1 ]
-; CHECK: br label %exit
define void @main(i1 %c) local_unnamed_addr #0 {
+; CHECK-LABEL: @main(
+; CHECK-NEXT: ph1:
+; CHECK-NEXT: br label [[H1:%.*]]
+; CHECK: h1:
+; CHECK-NEXT: [[D_0:%.*]] = phi i32 [ [[TMP0:%.*]], [[LATCH1:%.*]] ], [ undef, [[PH1:%.*]] ]
+; CHECK-NEXT: br label [[PH2:%.*]]
+; CHECK: ph2:
+; CHECK-NEXT: br label [[H2:%.*]]
+; CHECK: h2:
+; CHECK-NEXT: br label [[H3:%.*]]
+; CHECK: h3:
+; CHECK-NEXT: br i1 [[C:%.*]], label [[LATCH3:%.*]], label [[EXIT_LOOPEXIT:%.*]]
+; CHECK: latch3:
+; CHECK-NEXT: br i1 false, label [[EXIT3:%.*]], label [[H3]]
+; CHECK: exit3:
+; CHECK-NEXT: br label [[LATCH2:%.*]]
+; CHECK: latch2:
+; CHECK-NEXT: br label [[H3_1:%.*]]
+; CHECK: h3.1:
+; CHECK-NEXT: br i1 [[C]], label [[LATCH3_1:%.*]], label [[EXIT_LOOPEXIT1:%.*]]
+; CHECK: latch3.1:
+; CHECK-NEXT: br i1 false, label [[EXIT3_1:%.*]], label [[H3_1]]
+; CHECK: exit3.1:
+; CHECK-NEXT: br label [[LATCH2_1:%.*]]
+; CHECK: latch2.1:
+; CHECK-NEXT: br i1 [[C]], label [[LATCH1]], label [[PH2]]
+; CHECK: latch1:
+; CHECK-NEXT: [[TMP0]] = load i32, i32* @b, align 4
+; CHECK-NEXT: br label [[H1]]
+; CHECK: exit.loopexit:
+; CHECK-NEXT: [[D_0_LCSSA_PH:%.*]] = phi i32 [ [[D_0]], [[H3]] ]
+; CHECK-NEXT: br label [[EXIT:%.*]]
+; CHECK: exit.loopexit1:
+; CHECK-NEXT: [[D_0_LCSSA_PH2:%.*]] = phi i32 [ [[D_0]], [[H3_1]] ]
+; CHECK-NEXT: br label [[EXIT]]
+; CHECK: exit:
+; CHECK-NEXT: [[D_0_LCSSA:%.*]] = phi i32 [ [[D_0_LCSSA_PH]], [[EXIT_LOOPEXIT]] ], [ [[D_0_LCSSA_PH2]], [[EXIT_LOOPEXIT1]] ]
+; CHECK-NEXT: ret void
+;
ph1:
br label %h1