*/
#define TCG_TARGET_ARM 1
-#define TCG_TARGET_REG_BITS 32
#undef TCG_TARGET_WORDS_BIGENDIAN
#undef TCG_TARGET_STACK_GROWSUP
#define TCG_TARGET_HPPA 1
-#if defined(_PA_RISC1_1)
-#define TCG_TARGET_REG_BITS 32
-#else
+#if TCG_TARGET_REG_BITS != 32
#error unsupported
#endif
*/
#define TCG_TARGET_IA64 1
-#define TCG_TARGET_REG_BITS 64
-
/* We only map the first 64 registers */
#define TCG_TARGET_NB_REGS 64
enum {
*/
#define TCG_TARGET_MIPS 1
-#define TCG_TARGET_REG_BITS 32
#ifdef __MIPSEB__
# define TCG_TARGET_WORDS_BIGENDIAN
#endif
*/
#define TCG_TARGET_PPC 1
-#define TCG_TARGET_REG_BITS 32
#define TCG_TARGET_WORDS_BIGENDIAN
#define TCG_TARGET_NB_REGS 32
*/
#define TCG_TARGET_PPC64 1
-#define TCG_TARGET_REG_BITS 64
#define TCG_TARGET_WORDS_BIGENDIAN
#define TCG_TARGET_NB_REGS 32
*/
#define TCG_TARGET_S390 1
-#ifdef __s390x__
-#define TCG_TARGET_REG_BITS 64
-#else
-#define TCG_TARGET_REG_BITS 32
-#endif
-
#define TCG_TARGET_WORDS_BIGENDIAN
typedef enum TCGReg {
*/
#define TCG_TARGET_SPARC 1
-#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
-#define TCG_TARGET_REG_BITS 64
-#else
-#define TCG_TARGET_REG_BITS 32
-#endif
-
#define TCG_TARGET_WORDS_BIGENDIAN
#define TCG_TARGET_NB_REGS 32