New instruction (FSGSBASE) for AMD bdver3 architecture

From-SVN: r198916

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 33c2491..ee2d403 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-05-15  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
+
+       * config/i386/i386.c (processor_alias_table): Add instruction
+       FSGSBASE for AMD bdver3 architecture.
+
 2013-05-14  Jakub Jelinek  <jakub@redhat.com>
 
        * tree.c (warn_deprecated_use): Print file:line using locus color.

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index a5727a1..0ca338c 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -3000,7 +3000,7 @@ ix86_option_override_internal (bool main_args_p)
        | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
        | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
        | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE 
-       | PTA_XSAVEOPT},
+       | PTA_XSAVEOPT | PTA_FSGSBASE},
       {"btver1", PROCESSOR_BTVER1, CPU_GENERIC64,
        PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
        | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW