unsigned long get_pll_clk(int pllreg)
{
unsigned long r, m, p, s, mask, fout;
+ unsigned int freq;
switch (pllreg) {
case APLL:
s = r & 0x7;
if (cpu_is_s5pc110()) {
+ freq = CONFIG_SYS_CLK_FREQ_C110;
if (pllreg == APLL) {
if (s < 1)
s = 1;
- fout = m * (CONFIG_SYS_CLK_FREQ_C110 / (p * (1 << (s - 1))));
+ fout = m * (freq / (p * (1 << (s - 1))));
} else
- fout = m * (CONFIG_SYS_CLK_FREQ_C110 / (p * (1 << s)));
- } else
- fout = m * (CONFIG_SYS_CLK_FREQ_C100 / (p * (1 << s)));
+ fout = m * (freq / (p * (1 << s)));
+ } else {
+ freq = CONFIG_SYS_CLK_FREQ_C100;
+ fout = m * (freq / (p * (1 << s)));
+ }
return fout;
}
get_hclk_sys(CLK_M) / 1000000,
get_hclk_sys(CLK_D) / 1000000,
get_hclk_sys(CLK_P) / 1000000);
- printf("\tPclk: Msys %luMhz, Dsys %luMhz, Psys %luMhz\n",
+ printf("\tPclk: Msys %3luMhz, Dsys %3luMhz, Psys %3luMhz\n",
get_pclk_sys(CLK_M) / 1000000,
get_pclk_sys(CLK_D) / 1000000,
get_pclk_sys(CLK_P) / 1000000);