pan/va: Fix conservative branch handling

Mixed up lanes and conservative branch combine. Fix that.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15069>

diff --git a/src/panfrost/bifrost/valhall/ISA.xml b/src/panfrost/bifrost/valhall/ISA.xml
index 14f63c6..1655835 100644 (file)
--- a/src/panfrost/bifrost/valhall/ISA.xml
+++ b/src/panfrost/bifrost/valhall/ISA.xml
@@ -280,7 +280,7 @@
     <value>b3</value>
   </enum>
 
-  <enum name="Lane (32-bit)">
+  <enum name="Combine">
     <desc>
       Used for the lane select of `BRANCHZ`. To use an 8-bit condition, a
       separate `ICMP` is required to cast to 16-bit.
@@ -288,7 +288,8 @@
     <value default="true">none</value>
     <value>h0</value>
     <value>h1</value>
-    <reserved/>
+    <value>and</value>
+    <value>lowbits</value>
   </enum>
 
   <enum name="Lane (16-bit)" implied="true">
@@ -661,8 +662,9 @@
       source to a nonzero constant to implement a jump. May introduce
       divergence, so generally requires `.reconverge` flow control.
     </desc>
-    <src lane="37">Value to compare against zero</src>
+    <src combine="true">Value to compare against zero</src>
     <imm name="offset" start="8" size="27" signed="true"/>
+    <conservative/>
     <mod name="eq" start="36" size="1"/>
   </ins>
 
@@ -683,8 +685,9 @@
       Jump to an indirectly specified (absolute or relative) address. Used to
       jump to blend shaders at the end of a fragment shader.
     </desc>
-    <src>Value to compare against zero</src>
+    <src combine="true">Value to compare against zero</src>
     <src>Branch target</src>
+    <conservative/>
     <mod name="eq" start="36" size="1"/>
     <mod name="absolute" start="40" size="1"/>
   </ins>

diff --git a/src/panfrost/bifrost/valhall/asm.py b/src/panfrost/bifrost/valhall/asm.py
index 566c756..0ff1316 100644 (file)
--- a/src/panfrost/bifrost/valhall/asm.py
+++ b/src/panfrost/bifrost/valhall/asm.py
@@ -275,6 +275,11 @@ def parse_asm(line):
                 swizzled = True
                 val = enums[f'lane_{src.size}_bit'].bare_values.index(mod)
                 encoded |= (val << src.offset['lane'])
+            elif src.combine and mod in enums['combine'].bare_values:
+                die_if(swizzled, "Multiple swizzles specified")
+                swizzled = True
+                val = enums['combine'].bare_values.index(mod)
+                encoded |= (val << src.offset['combine'])
             elif src.size == 32 and mod in enums['widen'].bare_values:
                 die_if(not src.swizzle, "Instruction doesn't take widens")
                 die_if(swizzled, "Multiple swizzles specified")

diff --git a/src/panfrost/bifrost/valhall/disasm.py b/src/panfrost/bifrost/valhall/disasm.py
index bef71ee..99e8c9b 100644 (file)
--- a/src/panfrost/bifrost/valhall/disasm.py
+++ b/src/panfrost/bifrost/valhall/disasm.py
@@ -189,6 +189,8 @@ va_disasm_instr(FILE *fp, uint64_t instr)
             fputs(valhall_half_swizzles_8_bit[(instr >> ${src.offset['widen']}) & 0xF], fp);
 % elif src.widen:
                    fputs(valhall_swizzles_${src.size}_bit[(instr >> ${src.offset['widen']}) & 0xF], fp);
+% elif src.combine:
+            fputs(valhall_combine[(instr >> ${src.offset['combine']}) & 0x7], fp);
 % endif
 % if src.lane:
             fputs(valhall_lane_${src.size}_bit[(instr >> ${src.lane}) & 0x3], fp);

diff --git a/src/panfrost/bifrost/valhall/valhall.py b/src/panfrost/bifrost/valhall/valhall.py
index eab9982..2e740dc 100644 (file)
--- a/src/panfrost/bifrost/valhall/valhall.py
+++ b/src/panfrost/bifrost/valhall/valhall.py
@@ -98,7 +98,8 @@ def Flag(name, start):
 
 # Model a single instruction
 class Source:
-    def __init__(self, index, size, is_float = False, swizzle = False, halfswizzle = False, widen = False, lanes = False, lane = None, absneg = False, notted = False, name = ""):
+    def __init__(self, index, size, is_float = False, swizzle = False,
+            halfswizzle = False, widen = False, lanes = False, combine = False, lane = None, absneg = False, notted = False, name = ""):
         self.is_float = is_float or absneg
         self.size = size
         self.absneg = absneg
@@ -108,6 +109,7 @@ class Source:
         self.widen = widen
         self.lanes = lanes
         self.lane = lane
+        self.combine = combine
         self.name = name
 
         self.offset = {}
@@ -130,6 +132,9 @@ class Source:
             assert(size in [16, 32])
             self.offset['swizzle'] = 24 + ((2 - index) * 2)
             self.bits['swizzle'] = 2
+        if combine:
+            self.offset['combine'] = 37
+            self.bits['combine'] = 3
 
 class Dest:
     def __init__(self, name = ""):
@@ -215,6 +220,7 @@ def build_source(el, i, size):
             halfswizzle = el.get('halfswizzle', False),
             widen = el.get('widen', False),
             lanes = el.get('lanes', False),
+            combine = el.get('combine', False),
             lane = lane,
             notted = el.get('not', False),
             name = el.text or "")
@@ -354,6 +360,7 @@ MODIFIERS = {
     "clamp": Modifier("clamp", 32, 2),
     "sr_count": Modifier("staging_register_count", 33, 3, implied = True),
 
+    "conservative": Flag("conservative", 35),
     "subgroup": Modifier("subgroup_size", 36, 4),
     "update": Modifier("update_mode", 36, 2),
     "sample": Modifier("sample_mode", 38, 2),