radv: Remove has_previous_stage
authorKonstantin Seurer <konstantin.seurer@gmail.com>
Sun, 9 Apr 2023 09:46:50 +0000 (11:46 +0200)
committerMarge Bot <emma+marge@anholt.net>
Tue, 11 Apr 2023 06:24:17 +0000 (06:24 +0000)
MESA_SHADER_NONE implies that has_previous_stage is false.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22382>

src/amd/vulkan/radv_pipeline.c
src/amd/vulkan/radv_pipeline_rt.c
src/amd/vulkan/radv_shader.c
src/amd/vulkan/radv_shader_args.c
src/amd/vulkan/radv_shader_args.h

index a6215c4..977fbe2 100644 (file)
@@ -2363,8 +2363,8 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
 
    if (gfx_level >= GFX9 && stages[MESA_SHADER_TESS_CTRL].nir) {
       radv_declare_shader_args(device, pipeline_key, &stages[MESA_SHADER_TESS_CTRL].info,
-                               MESA_SHADER_TESS_CTRL, true, MESA_SHADER_VERTEX,
-                               RADV_SHADER_TYPE_DEFAULT, &stages[MESA_SHADER_TESS_CTRL].args);
+                               MESA_SHADER_TESS_CTRL, MESA_SHADER_VERTEX, RADV_SHADER_TYPE_DEFAULT,
+                               &stages[MESA_SHADER_TESS_CTRL].args);
       stages[MESA_SHADER_TESS_CTRL].info.user_sgprs_locs = stages[MESA_SHADER_TESS_CTRL].args.user_sgprs_locs;
       stages[MESA_SHADER_TESS_CTRL].info.inline_push_constant_mask =
          stages[MESA_SHADER_TESS_CTRL].args.ac.inline_push_const_mask;
@@ -2381,7 +2381,7 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
       gl_shader_stage pre_stage =
          stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
       radv_declare_shader_args(device, pipeline_key, &stages[MESA_SHADER_GEOMETRY].info,
-                               MESA_SHADER_GEOMETRY, true, pre_stage, RADV_SHADER_TYPE_DEFAULT,
+                               MESA_SHADER_GEOMETRY, pre_stage, RADV_SHADER_TYPE_DEFAULT,
                                &stages[MESA_SHADER_GEOMETRY].args);
       stages[MESA_SHADER_GEOMETRY].info.user_sgprs_locs = stages[MESA_SHADER_GEOMETRY].args.user_sgprs_locs;
       stages[MESA_SHADER_GEOMETRY].info.inline_push_constant_mask =
@@ -2395,7 +2395,7 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
    }
 
    u_foreach_bit(i, active_nir_stages) {
-      radv_declare_shader_args(device, pipeline_key, &stages[i].info, i, false, MESA_SHADER_VERTEX,
+      radv_declare_shader_args(device, pipeline_key, &stages[i].info, i, MESA_SHADER_NONE,
                                RADV_SHADER_TYPE_DEFAULT, &stages[i].args);
       stages[i].info.user_sgprs_locs = stages[i].args.user_sgprs_locs;
       stages[i].info.inline_push_constant_mask = stages[i].args.ac.inline_push_const_mask;
@@ -2667,8 +2667,8 @@ radv_pipeline_create_gs_copy_shader(struct radv_device *device, struct radv_pipe
    gs_copy_stage.info.outinfo = gs_info->outinfo;
    gs_copy_stage.info.force_vrs_per_vertex = gs_info->force_vrs_per_vertex;
 
-   radv_declare_shader_args(device, pipeline_key, &gs_copy_stage.info, MESA_SHADER_VERTEX, false,
-                            MESA_SHADER_VERTEX, RADV_SHADER_TYPE_GS_COPY, &gs_copy_stage.args);
+   radv_declare_shader_args(device, pipeline_key, &gs_copy_stage.info, MESA_SHADER_VERTEX,
+                            MESA_SHADER_NONE, RADV_SHADER_TYPE_GS_COPY, &gs_copy_stage.args);
    gs_copy_stage.info.user_sgprs_locs = gs_copy_stage.args.user_sgprs_locs;
    gs_copy_stage.info.inline_push_constant_mask = gs_copy_stage.args.ac.inline_push_const_mask;
 
@@ -5153,8 +5153,8 @@ radv_compute_pipeline_compile(struct radv_compute_pipeline *pipeline,
    radv_nir_shader_info_pass(device, cs_stage.nir, MESA_SHADER_NONE, pipeline_layout, pipeline_key,
                              pipeline->base.type, false, &cs_stage.info);
 
-   radv_declare_shader_args(device, pipeline_key, &cs_stage.info, MESA_SHADER_COMPUTE, false,
-                            MESA_SHADER_VERTEX, RADV_SHADER_TYPE_DEFAULT, &cs_stage.args);
+   radv_declare_shader_args(device, pipeline_key, &cs_stage.info, MESA_SHADER_COMPUTE,
+                            MESA_SHADER_NONE, RADV_SHADER_TYPE_DEFAULT, &cs_stage.args);
 
    cs_stage.info.user_sgprs_locs = cs_stage.args.user_sgprs_locs;
    cs_stage.info.inline_push_constant_mask = cs_stage.args.ac.inline_push_const_mask;
index bbe9afd..0bc7b7f 100644 (file)
@@ -266,8 +266,8 @@ radv_rt_pipeline_compile(struct radv_ray_tracing_pipeline *pipeline,
    radv_nir_shader_info_pass(device, rt_stage.nir, MESA_SHADER_NONE, pipeline_layout, pipeline_key,
                              pipeline->base.base.type, false, &rt_stage.info);
 
-   radv_declare_shader_args(device, pipeline_key, &rt_stage.info, rt_stage.stage, false,
-                            MESA_SHADER_NONE, RADV_SHADER_TYPE_DEFAULT, &rt_stage.args);
+   radv_declare_shader_args(device, pipeline_key, &rt_stage.info, rt_stage.stage, MESA_SHADER_NONE,
+                            RADV_SHADER_TYPE_DEFAULT, &rt_stage.args);
 
    rt_stage.info.user_sgprs_locs = rt_stage.args.user_sgprs_locs;
    rt_stage.info.inline_push_constant_mask = rt_stage.args.ac.inline_push_const_mask;
index e3e6b68..f308dfa 100644 (file)
@@ -2283,7 +2283,7 @@ radv_create_trap_handler_shader(struct radv_device *device)
    info.wave_size = 64;
 
    struct radv_shader_args args;
-   radv_declare_shader_args(device, &key, &info, stage, false, MESA_SHADER_NONE,
+   radv_declare_shader_args(device, &key, &info, stage, MESA_SHADER_NONE,
                             RADV_SHADER_TYPE_TRAP_HANDLER, &args);
 
    struct radv_shader_binary *binary =
@@ -2354,8 +2354,8 @@ radv_create_rt_prolog(struct radv_device *device)
 
    struct radv_pipeline_key pipeline_key = {0};
 
-   radv_declare_shader_args(device, &pipeline_key, &info, MESA_SHADER_COMPUTE, false,
-                            MESA_SHADER_NONE, RADV_SHADER_TYPE_DEFAULT, &in_args);
+   radv_declare_shader_args(device, &pipeline_key, &info, MESA_SHADER_COMPUTE, MESA_SHADER_NONE,
+                            RADV_SHADER_TYPE_DEFAULT, &in_args);
    radv_declare_rt_shader_args(options.gfx_level, &out_args);
    info.user_sgprs_locs = in_args.user_sgprs_locs;
 
@@ -2418,9 +2418,10 @@ radv_create_vs_prolog(struct radv_device *device, const struct radv_vs_prolog_ke
 
    struct radv_pipeline_key pipeline_key = {0};
 
-   radv_declare_shader_args(device, &pipeline_key, &info, key->next_stage,
-                            key->next_stage != MESA_SHADER_VERTEX, MESA_SHADER_VERTEX,
-                            RADV_SHADER_TYPE_DEFAULT, &args);
+   radv_declare_shader_args(
+      device, &pipeline_key, &info, key->next_stage,
+      key->next_stage != MESA_SHADER_VERTEX ? MESA_SHADER_VERTEX : MESA_SHADER_NONE,
+      RADV_SHADER_TYPE_DEFAULT, &args);
 
    info.user_sgprs_locs = args.user_sgprs_locs;
    info.inline_push_constant_mask = args.ac.inline_push_const_mask;
index 63891d0..c51b9bb 100644 (file)
@@ -137,15 +137,13 @@ declare_global_input_sgprs(const struct radv_shader_info *info,
 
 static void
 declare_vs_specific_input_sgprs(const struct radv_shader_info *info, struct radv_shader_args *args,
-                                gl_shader_stage stage, bool has_previous_stage,
-                                gl_shader_stage previous_stage)
+                                gl_shader_stage stage, gl_shader_stage previous_stage)
 {
    if (info->vs.has_prolog)
       add_ud_arg(args, 2, AC_ARG_INT, &args->prolog_inputs, AC_UD_VS_PROLOG_INPUTS);
 
    if (args->type != RADV_SHADER_TYPE_GS_COPY &&
-       (stage == MESA_SHADER_VERTEX ||
-        (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
+       (stage == MESA_SHADER_VERTEX || previous_stage == MESA_SHADER_VERTEX)) {
       if (info->vs.vb_desc_usage_mask) {
          add_ud_arg(args, 1, AC_ARG_CONST_DESC_PTR, &args->ac.vertex_buffers,
                     AC_UD_VS_VERTEX_BUFFERS);
@@ -371,9 +369,8 @@ radv_declare_rt_shader_args(enum amd_gfx_level gfx_level, struct radv_shader_arg
 static void
 declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key,
                     const struct radv_shader_info *info, gl_shader_stage stage,
-                    bool has_previous_stage, gl_shader_stage previous_stage,
-                    enum radv_shader_type type, struct radv_shader_args *args,
-                    struct user_sgpr_info *user_sgpr_info)
+                    gl_shader_stage previous_stage, enum radv_shader_type type,
+                    struct radv_shader_args *args, struct user_sgpr_info *user_sgpr_info)
 {
    const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
    bool needs_view_index = info->uses_view_index;
@@ -386,7 +383,6 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
       /* Handle all NGG shaders as GS to simplify the code here. */
       previous_stage = stage;
       stage = MESA_SHADER_GEOMETRY;
-      has_previous_stage = true;
    }
 
    radv_init_shader_args(device, stage, type, args);
@@ -405,7 +401,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
    /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
     * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0.
     */
-   if (has_previous_stage)
+   if (previous_stage != MESA_SHADER_NONE)
       args->num_user_sgprs = 0;
 
    /* To ensure prologs match the main VS, VS specific input SGPRs have to be placed before other
@@ -466,7 +462,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
       /* NGG is handled by the GS case */
       assert(!info->is_ngg);
 
-      declare_vs_specific_input_sgprs(info, args, stage, has_previous_stage, previous_stage);
+      declare_vs_specific_input_sgprs(info, args, stage, previous_stage);
 
       declare_global_input_sgprs(info, user_sgpr_info, args);
 
@@ -493,7 +489,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
       declare_vs_input_vgprs(gfx_level, info, args, false);
       break;
    case MESA_SHADER_TESS_CTRL:
-      if (has_previous_stage) {
+      if (previous_stage != MESA_SHADER_NONE) {
          // First 6 system regs
          ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset);
          ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.merged_wave_info);
@@ -508,7 +504,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
          ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); // unknown
          ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); // unknown
 
-         declare_vs_specific_input_sgprs(info, args, stage, has_previous_stage, previous_stage);
+         declare_vs_specific_input_sgprs(info, args, stage, previous_stage);
 
          declare_global_input_sgprs(info, user_sgpr_info, args);
 
@@ -570,7 +566,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
       declare_tes_input_vgprs(args);
       break;
    case MESA_SHADER_GEOMETRY:
-      if (has_previous_stage) {
+      if (previous_stage != MESA_SHADER_NONE) {
          // First 6 system regs
          if (info->is_ngg) {
             ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.gs_tg_info);
@@ -591,7 +587,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
          ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); // unknown
 
          if (previous_stage == MESA_SHADER_VERTEX) {
-            declare_vs_specific_input_sgprs(info, args, stage, has_previous_stage, previous_stage);
+            declare_vs_specific_input_sgprs(info, args, stage, previous_stage);
          } else if (previous_stage == MESA_SHADER_MESH) {
             declare_ms_input_sgprs(info, args);
          }
@@ -682,11 +678,10 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
 void
 radv_declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key,
                          const struct radv_shader_info *info, gl_shader_stage stage,
-                         bool has_previous_stage, gl_shader_stage previous_stage,
-                         enum radv_shader_type type, struct radv_shader_args *args)
+                         gl_shader_stage previous_stage, enum radv_shader_type type,
+                         struct radv_shader_args *args)
 {
-   declare_shader_args(device, key, info, stage, has_previous_stage, previous_stage, type, args,
-                       NULL);
+   declare_shader_args(device, key, info, stage, previous_stage, type, args, NULL);
 
    if (gl_shader_stage_is_rt(stage))
       return;
@@ -715,8 +710,7 @@ radv_declare_shader_args(const struct radv_device *device, const struct radv_pip
 
    allocate_inline_push_consts(info, &user_sgpr_info);
 
-   declare_shader_args(device, key, info, stage, has_previous_stage, previous_stage, type, args,
-                       &user_sgpr_info);
+   declare_shader_args(device, key, info, stage, previous_stage, type, args, &user_sgpr_info);
 }
 
 void
index 9092510..e3fb771 100644 (file)
@@ -99,8 +99,8 @@ struct radv_shader_info;
 
 void radv_declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key,
                               const struct radv_shader_info *info, gl_shader_stage stage,
-                              bool has_previous_stage, gl_shader_stage previous_stage,
-                              enum radv_shader_type type, struct radv_shader_args *args);
+                              gl_shader_stage previous_stage, enum radv_shader_type type,
+                              struct radv_shader_args *args);
 
 void radv_declare_ps_epilog_args(const struct radv_device *device,
                                  const struct radv_ps_epilog_key *key,