projects
/
platform
/
upstream
/
llvm.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
ad1d023
)
[X86][AVX512] Tag CLWB instruction to CLFLUSH/PREFETCH scheduler class
author
Simon Pilgrim
<llvm-dev@redking.me.uk>
Fri, 8 Dec 2017 15:19:10 +0000
(15:19 +0000)
committer
Simon Pilgrim
<llvm-dev@redking.me.uk>
Fri, 8 Dec 2017 15:19:10 +0000
(15:19 +0000)
llvm-svn: 320156
llvm/lib/Target/X86/X86InstrInfo.td
patch
|
blob
|
history
diff --git
a/llvm/lib/Target/X86/X86InstrInfo.td
b/llvm/lib/Target/X86/X86InstrInfo.td
index 1a495bf56df14cfee3fd29428aa4232f0429ee44..eed129a1fa005fcdcfb8b42b131c2c7d1a1f2891 100644
(file)
--- a/
llvm/lib/Target/X86/X86InstrInfo.td
+++ b/
llvm/lib/Target/X86/X86InstrInfo.td
@@
-2723,10
+2723,9
@@
def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
"clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
IIC_SSE_PREFETCH>, PD;
-let Predicates = [HasCLWB] in
+let Predicates = [HasCLWB]
, SchedRW = [WriteLoad]
in
def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src",
- [(int_x86_clwb addr:$src)]>, PD;
-
+ [(int_x86_clwb addr:$src)], IIC_SSE_PREFETCH>, PD;
//===----------------------------------------------------------------------===//
// Subsystems.