projects / platform / upstream / llvm.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: a453f36)
[X86] Add the rest of the TEST with immediate instructions to the scheduler models...
authorCraig Topper <craig.topper@intel.com>
Mon, 19 Mar 2018 17:58:41 +0000 (17:58 +0000)
committerCraig Topper <craig.topper@intel.com>
Mon, 19 Mar 2018 17:58:41 +0000 (17:58 +0000)
llvm-svn: 327874

llvm/lib/Target/X86/X86SchedBroadwell.td patch | blob | history
llvm/lib/Target/X86/X86SchedHaswell.td patch | blob | history
llvm/lib/Target/X86/X86SchedSandyBridge.td patch | blob | history
llvm/lib/Target/X86/X86SchedSkylakeClient.td patch | blob | history
llvm/lib/Target/X86/X86SchedSkylakeServer.td patch | blob | history

diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 856e5c6..bd06a27 100755 (executable)
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -840,8 +840,8 @@ def: InstRW<[BWWriteResGroup9], (instregex "SUB(8|16|32|64)rr")>;
 def: InstRW<[BWWriteResGroup9], (instregex "SUB(8|16|32|64)i")>;
 def: InstRW<[BWWriteResGroup9], (instregex "SYSCALL")>;
 def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "TEST8i8")>;
-def: InstRW<[BWWriteResGroup9], (instregex "TEST8ri")>;
+def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)i")>;
+def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "XCHG(16|32|64)rr")>;
 def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)rr")>;
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index e2559a4..cac3a3b 100644 (file)
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -1256,8 +1256,8 @@ def: InstRW<[HWWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SUB(8|16|32|64)i")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SYSCALL")>;
 def: InstRW<[HWWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup10], (instregex "TEST8i8")>;
-def: InstRW<[HWWriteResGroup10], (instregex "TEST8ri")>;
+def: InstRW<[HWWriteResGroup10], (instregex "TEST(8|16|32|64)i")>;
+def: InstRW<[HWWriteResGroup10], (instregex "TEST(8|16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
 def: InstRW<[HWWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index a8372e7..e8b259c 100644 (file)
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -649,8 +649,8 @@ def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)rr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)i")>;
 def: InstRW<[SBWriteResGroup6], (instregex "TEST(8|16|32|64)rr")>;
-def: InstRW<[SBWriteResGroup6], (instregex "TEST8i8")>;
-def: InstRW<[SBWriteResGroup6], (instregex "TEST8ri")>;
+def: InstRW<[SBWriteResGroup6], (instregex "TEST(8|16|32|64)i")>;
+def: InstRW<[SBWriteResGroup6], (instregex "TEST(8|16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "VMOVPQI2QIrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "VMOVZPQILo2PQIrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "VPANDNrr")>;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index 1891f13..01b87bc 100644 (file)
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -846,8 +846,8 @@ def: InstRW<[SKLWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "SUB(8|16|32|64)i")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "SYSCALL")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "TEST8i8")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "TEST8ri")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "TEST(8|16|32|64)i")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "TEST(8|16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index 42de233..72fff2d 100755 (executable)
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -1276,8 +1276,8 @@ def: InstRW<[SKXWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "SUB(8|16|32|64)i")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "SYSCALL")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "TEST8i8")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "TEST8ri")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "TEST(8|16|32|64)i")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "TEST(8|16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;
Domain: System / Toolchain;