return false;
}
+// Determines if it is a constant integer of all ones or a splatted vector of a
+// constant integer of all ones (with no undefs).
+// Do not permit build vector implicit truncation.
+static bool isAllOnesConstantOrAllOnesSplatConstant(SDValue N) {
+ unsigned BitWidth = N.getScalarValueSizeInBits();
+ if (ConstantSDNode *Splat = isConstOrConstSplat(N))
+ return Splat->isAllOnesValue() &&
+ Splat->getAPIntValue().getBitWidth() == BitWidth;
+ return false;
+}
+
SDValue DAGCombiner::ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
SDValue N1) {
EVT VT = N0.getValueType();
}
// Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
- if (isAllOnesConstant(N0))
+ if (isAllOnesConstantOrAllOnesSplatConstant(N0))
return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
// fold A-(A-B) -> B
; SSE-LABEL: combine_vec_sub_negone:
; SSE: # BB#0:
; SSE-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE-NEXT: psubd %xmm0, %xmm1
-; SSE-NEXT: movdqa %xmm1, %xmm0
+; SSE-NEXT: pxor %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_sub_negone:
; AVX: # BB#0:
; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = sub <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %x
ret <4 x i32> %1