* config/tc-arm.c (literal_pool): New field "alignment".
(find_or_make_literal_pool): Initialize "alignment" to 2.
(s_ltorg): Align the pool using value of "alignment"
(parse_big_immediate): New parameter "in_exp". Return
parsed expression if "in_exp" is not null.
(parse_address_main): Invoke "parse_big_immediate" for
constant parameter.
(add_to_lit_pool): Add one parameter 'nbytes'.
Split 8 byte entry into two 4 byte entry.
Add padding to align 8 byte entry to 8 byte boundary.
(encode_arm_cp_address): Generate literal pool entry if possible.
(move_or_literal_pool): Generate entry for vldr case.
(enum lit_type): New enum type.
(do_ldst): Use new enum type.
(do_ldstv4): Likewise.
(do_t_ldst): Likewise.
(neon_write_immbits): Support Thumb-2 mode.
* gas/arm/ldconst.s: Add test cases for symbol literal.
* gas/arm/ldconst.d: Likewise.
* gas/arm/vldconst.s: Add test cases for vldr.
* gas/arm/thumb2_vpool.s: Likewise.
* gas/arm/vldconst.d: New pattern for little-endian.
* gas/arm/thumb2_vpool.d: Likewise.
* gas/arm/vldconst_be.d: New pattern for big-endian.
* gas/arm/thumb2_vpool_be.d: Likewise.
+2014-07-08 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-arm.c (literal_pool): New field "alignment".
+ (find_or_make_literal_pool): Initialize "alignment" to 2.
+ (s_ltorg): Align the pool using value of "alignment"
+ (parse_big_immediate): New parameter "in_exp". Return
+ parsed expression if "in_exp" is not null.
+ (parse_address_main): Invoke "parse_big_immediate" for
+ constant parameter.
+ (add_to_lit_pool): Add one parameter 'nbytes'.
+ Split 8 byte entry into two 4 byte entry.
+ Add padding to align 8 byte entry to 8 byte boundary.
+ (encode_arm_cp_address): Generate literal pool entry if possible.
+ (move_or_literal_pool): Generate entry for vldr case.
+ (enum lit_type): New enum type.
+ (do_ldst): Use new enum type.
+ (do_ldstv4): Likewise.
+ (do_t_ldst): Likewise.
+ (neon_write_immbits): Support Thumb-2 mode.
+
2014-07-07 Barney Stratford <barney_stratford@fastmail.fm>
* config/tc-avr.c (avr_operand): Permit referring to r26-r31 by
#define LITERAL_MASK 0xf000f000
#define OPCODE_MASK 0xfe1fffff
#define V4_STR_BIT 0x00000020
+#define VLDR_VMOV_SAME 0x0040f000
#define T2_SUBS_PC_LR 0xf3de8f00
struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
#endif
struct literal_pool * next;
+ unsigned int alignment;
} literal_pool;
/* Pointer to a linked list of literal pools. */
pool->sub_section = now_subseg;
pool->next = list_of_pools;
pool->symbol = NULL;
+ pool->alignment = 2;
/* Add it to the list. */
list_of_pools = pool;
structure to the relevant literal pool. */
static int
-add_to_lit_pool (void)
+add_to_lit_pool (unsigned int nbytes)
{
+#define PADDING_SLOT 0x1
+#define LIT_ENTRY_SIZE_MASK 0xFF
literal_pool * pool;
- unsigned int entry;
+ unsigned int entry, pool_size = 0;
+ bfd_boolean padding_slot_p = FALSE;
+ unsigned imm1;
+ unsigned imm2 = 0;
+
+ if (nbytes == 8)
+ {
+ imm1 = inst.operands[1].imm;
+ imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
+ : inst.reloc.exp.X_unsigned ? 0
+ : ((int64_t)(imm1)) >> 32);
+ if (target_big_endian)
+ {
+ imm1 = imm2;
+ imm2 = inst.operands[1].imm;
+ }
+ }
pool = find_or_make_literal_pool ();
/* Check if this literal value is already in the pool. */
for (entry = 0; entry < pool->next_free_entry; entry ++)
{
- if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
- && (inst.reloc.exp.X_op == O_constant)
- && (pool->literals[entry].X_add_number
- == inst.reloc.exp.X_add_number)
- && (pool->literals[entry].X_unsigned
- == inst.reloc.exp.X_unsigned))
+ if (nbytes == 4)
+ {
+ if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
+ && (inst.reloc.exp.X_op == O_constant)
+ && (pool->literals[entry].X_add_number
+ == inst.reloc.exp.X_add_number)
+ && (pool->literals[entry].X_md == nbytes)
+ && (pool->literals[entry].X_unsigned
+ == inst.reloc.exp.X_unsigned))
+ break;
+
+ if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
+ && (inst.reloc.exp.X_op == O_symbol)
+ && (pool->literals[entry].X_add_number
+ == inst.reloc.exp.X_add_number)
+ && (pool->literals[entry].X_add_symbol
+ == inst.reloc.exp.X_add_symbol)
+ && (pool->literals[entry].X_op_symbol
+ == inst.reloc.exp.X_op_symbol)
+ && (pool->literals[entry].X_md == nbytes))
+ break;
+ }
+ else if ((nbytes == 8)
+ && !(pool_size & 0x7)
+ && ((entry + 1) != pool->next_free_entry)
+ && (pool->literals[entry].X_op == O_constant)
+ && (pool->literals[entry].X_add_number == imm1)
+ && (pool->literals[entry].X_unsigned
+ == inst.reloc.exp.X_unsigned)
+ && (pool->literals[entry + 1].X_op == O_constant)
+ && (pool->literals[entry + 1].X_add_number == imm2)
+ && (pool->literals[entry + 1].X_unsigned
+ == inst.reloc.exp.X_unsigned))
break;
- if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
- && (inst.reloc.exp.X_op == O_symbol)
- && (pool->literals[entry].X_add_number
- == inst.reloc.exp.X_add_number)
- && (pool->literals[entry].X_add_symbol
- == inst.reloc.exp.X_add_symbol)
- && (pool->literals[entry].X_op_symbol
- == inst.reloc.exp.X_op_symbol))
+ padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
+ if (padding_slot_p && (nbytes == 4))
break;
+
+ pool_size += 4;
}
/* Do we need to create a new entry? */
return FAIL;
}
- pool->literals[entry] = inst.reloc.exp;
+ if (nbytes == 8)
+ {
+ /* For 8-byte entries, we align to an 8-byte boundary,
+ and split it into two 4-byte entries, because on 32-bit
+ host, 8-byte constants are treated as big num, thus
+ saved in "generic_bignum" which will be overwritten
+ by later assignments.
+
+ We also need to make sure there is enough space for
+ the split.
+
+ We also check to make sure the literal operand is a
+ constant number. */
+ if (!(inst.reloc.exp.X_op == O_constant)
+ || (inst.reloc.exp.X_op == O_big))
+ {
+ inst.error = _("invalid type for literal pool");
+ return FAIL;
+ }
+ else if (pool_size & 0x7)
+ {
+ if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
+ {
+ inst.error = _("literal pool overflow");
+ return FAIL;
+ }
+
+ pool->literals[entry] = inst.reloc.exp;
+ pool->literals[entry].X_add_number = 0;
+ pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
+ pool->next_free_entry += 1;
+ pool_size += 4;
+ }
+ else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
+ {
+ inst.error = _("literal pool overflow");
+ return FAIL;
+ }
+
+ pool->literals[entry] = inst.reloc.exp;
+ pool->literals[entry].X_op = O_constant;
+ pool->literals[entry].X_add_number = imm1;
+ pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
+ pool->literals[entry++].X_md = 4;
+ pool->literals[entry] = inst.reloc.exp;
+ pool->literals[entry].X_op = O_constant;
+ pool->literals[entry].X_add_number = imm2;
+ pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
+ pool->literals[entry].X_md = 4;
+ pool->alignment = 3;
+ pool->next_free_entry += 1;
+ }
+ else
+ {
+ pool->literals[entry] = inst.reloc.exp;
+ pool->literals[entry].X_md = 4;
+ }
+
#ifdef OBJ_ELF
/* PR ld/12974: Record the location of the first source line to reference
this entry in the literal pool. If it turns out during linking that the
#endif
pool->next_free_entry += 1;
}
+ else if (padding_slot_p)
+ {
+ pool->literals[entry] = inst.reloc.exp;
+ pool->literals[entry].X_md = nbytes;
+ }
inst.reloc.exp.X_op = O_symbol;
- inst.reloc.exp.X_add_number = ((int) entry) * 4;
+ inst.reloc.exp.X_add_number = pool_size;
inst.reloc.exp.X_add_symbol = pool->symbol;
return SUCCESS;
#endif /* DEBUG_SYMS */
}
-
static void
s_ltorg (int ignored ATTRIBUTE_UNUSED)
{
/* Align pool as you have word accesses.
Only make a frag if we have to. */
if (!need_pass_2)
- frag_align (2, 0, 0);
+ frag_align (pool->alignment, 0, 0);
record_alignment (now_seg, 2);
dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
#endif
/* First output the expression in the instruction to the pool. */
- emit_expr (&(pool->literals[entry]), 4); /* .word */
+ emit_expr (&(pool->literals[entry]),
+ pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
}
/* Mark the pool as empty. */
instructions. Puts the result directly in inst.operands[i]. */
static int
-parse_big_immediate (char **str, int i)
+parse_big_immediate (char **str, int i, expressionS *in_exp,
+ bfd_boolean allow_symbol_p)
{
expressionS exp;
+ expressionS *exp_p = in_exp ? in_exp : &exp;
char *ptr = *str;
- my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
+ my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
- if (exp.X_op == O_constant)
+ if (exp_p->X_op == O_constant)
{
- inst.operands[i].imm = exp.X_add_number & 0xffffffff;
+ inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
/* If we're on a 64-bit host, then a 64-bit number can be returned using
O_constant. We have to be careful not to break compilation for
32-bit X_add_number, though. */
- if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
+ if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
{
- /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
- inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
+ /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
+ inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
+ & 0xffffffff);
inst.operands[i].regisimm = 1;
}
}
- else if (exp.X_op == O_big
- && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
+ else if (exp_p->X_op == O_big
+ && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
{
unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
PR 11972: Bignums can now be sign-extended to the
size of a .octa so check that the out of range bits
are all zero or all one. */
- if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
+ if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
{
LITTLENUM_TYPE m = -1;
&& generic_bignum[parts * 2] != m)
return FAIL;
- for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
+ for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
if (generic_bignum[j] != generic_bignum[j-1])
return FAIL;
}
<< (LITTLENUM_NUMBER_OF_BITS * j);
inst.operands[i].regisimm = 1;
}
- else
+ else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
return FAIL;
*str = ptr;
inst.operands[i].reg = REG_PC;
inst.operands[i].isreg = 1;
inst.operands[i].preind = 1;
- }
- /* Otherwise a load-constant pseudo op, no special treatment needed here. */
- if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
+ if (my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX_BIG))
+ return PARSE_OPERAND_FAIL;
+ }
+ else if (parse_big_immediate (&p, i, &inst.reloc.exp,
+ /*allow_symbol_p=*/TRUE))
return PARSE_OPERAND_FAIL;
*str = p;
Case 10: VMOV.F32 <Sd>, #<imm>
Case 11: VMOV.F64 <Dd>, #<imm> */
inst.operands[i].immisfloat = 1;
- else if (parse_big_immediate (&ptr, i) == SUCCESS)
+ else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
+ == SUCCESS)
/* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
;
try_immbig:
/* There's a possibility of getting a 64-bit immediate here, so
we need special handling. */
- if (parse_big_immediate (&str, i) == FAIL)
+ if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
+ == FAIL)
{
inst.error = _("immediate value is out of range");
goto failure;
}
}
-/* inst.operands[i] was set up by parse_address. Encode it into an
- ARM-format instruction. Reject all forms which cannot be encoded
- into a coprocessor load/store instruction. If wb_ok is false,
- reject use of writeback; if unind_ok is false, reject use of
- unindexed addressing. If reloc_override is not 0, use it instead
- of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
- (in which case it is preserved). */
+/* Write immediate bits [7:0] to the following locations:
+
+ |28/24|23 19|18 16|15 4|3 0|
+ | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
+
+ This function is used by VMOV/VMVN/VORR/VBIC. */
+
+static void
+neon_write_immbits (unsigned immbits)
+{
+ inst.instruction |= immbits & 0xf;
+ inst.instruction |= ((immbits >> 4) & 0x7) << 16;
+ inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
+}
+
+/* Invert low-order SIZE bits of XHI:XLO. */
+
+static void
+neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
+{
+ unsigned immlo = xlo ? *xlo : 0;
+ unsigned immhi = xhi ? *xhi : 0;
+
+ switch (size)
+ {
+ case 8:
+ immlo = (~immlo) & 0xff;
+ break;
+
+ case 16:
+ immlo = (~immlo) & 0xffff;
+ break;
+
+ case 64:
+ immhi = (~immhi) & 0xffffffff;
+ /* fall through. */
+
+ case 32:
+ immlo = (~immlo) & 0xffffffff;
+ break;
+
+ default:
+ abort ();
+ }
+
+ if (xlo)
+ *xlo = immlo;
+
+ if (xhi)
+ *xhi = immhi;
+}
+
+/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
+ A, B, C, D. */
static int
-encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
+neon_bits_same_in_bytes (unsigned imm)
{
- inst.instruction |= inst.operands[i].reg << 16;
+ return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
+ && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
+ && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
+ && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
+}
- gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
+/* For immediate of above form, return 0bABCD. */
- if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
+static unsigned
+neon_squash_bits (unsigned imm)
+{
+ return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
+ | ((imm & 0x01000000) >> 21);
+}
+
+/* Compress quarter-float representation to 0b...000 abcdefgh. */
+
+static unsigned
+neon_qfloat_bits (unsigned imm)
+{
+ return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
+}
+
+/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
+ the instruction. *OP is passed as the initial value of the op field, and
+ may be set to a different value depending on the constant (i.e.
+ "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
+ MVN). If the immediate looks like a repeated pattern then also
+ try smaller element sizes. */
+
+static int
+neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
+ unsigned *immbits, int *op, int size,
+ enum neon_el_type type)
+{
+ /* Only permit float immediates (including 0.0/-0.0) if the operand type is
+ float. */
+ if (type == NT_float && !float_p)
+ return FAIL;
+
+ if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
{
- gas_assert (!inst.operands[i].writeback);
- if (!unind_ok)
+ if (size != 32 || *op == 1)
+ return FAIL;
+ *immbits = neon_qfloat_bits (immlo);
+ return 0xf;
+ }
+
+ if (size == 64)
+ {
+ if (neon_bits_same_in_bytes (immhi)
+ && neon_bits_same_in_bytes (immlo))
{
- inst.error = _("instruction does not support unindexed addressing");
- return FAIL;
+ if (*op == 1)
+ return FAIL;
+ *immbits = (neon_squash_bits (immhi) << 4)
+ | neon_squash_bits (immlo);
+ *op = 1;
+ return 0xe;
}
- inst.instruction |= inst.operands[i].imm;
- inst.instruction |= INDEX_UP;
- return SUCCESS;
- }
- if (inst.operands[i].preind)
- inst.instruction |= PRE_INDEX;
+ if (immhi != immlo)
+ return FAIL;
+ }
- if (inst.operands[i].writeback)
+ if (size >= 32)
{
- if (inst.operands[i].reg == REG_PC)
+ if (immlo == (immlo & 0x000000ff))
{
- inst.error = _("pc may not be used with write-back");
- return FAIL;
+ *immbits = immlo;
+ return 0x0;
}
- if (!wb_ok)
+ else if (immlo == (immlo & 0x0000ff00))
{
- inst.error = _("instruction does not support writeback");
- return FAIL;
+ *immbits = immlo >> 8;
+ return 0x2;
}
- inst.instruction |= WRITE_BACK;
+ else if (immlo == (immlo & 0x00ff0000))
+ {
+ *immbits = immlo >> 16;
+ return 0x4;
+ }
+ else if (immlo == (immlo & 0xff000000))
+ {
+ *immbits = immlo >> 24;
+ return 0x6;
+ }
+ else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
+ {
+ *immbits = (immlo >> 8) & 0xff;
+ return 0xc;
+ }
+ else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
+ {
+ *immbits = (immlo >> 16) & 0xff;
+ return 0xd;
+ }
+
+ if ((immlo & 0xffff) != (immlo >> 16))
+ return FAIL;
+ immlo &= 0xffff;
}
- if (reloc_override)
- inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
- else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
- || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
- && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
+ if (size >= 16)
{
- if (thumb_mode)
- inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
- else
- inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
+ if (immlo == (immlo & 0x000000ff))
+ {
+ *immbits = immlo;
+ return 0x8;
+ }
+ else if (immlo == (immlo & 0x0000ff00))
+ {
+ *immbits = immlo >> 8;
+ return 0xa;
+ }
+
+ if ((immlo & 0xff) != (immlo >> 8))
+ return FAIL;
+ immlo &= 0xff;
}
- /* Prefer + for zero encoded value. */
- if (!inst.operands[i].negative)
- inst.instruction |= INDEX_UP;
+ if (immlo == (immlo & 0x000000ff))
+ {
+ /* Don't allow MVN with 8-bit immediate. */
+ if (*op == 1)
+ return FAIL;
+ *immbits = immlo;
+ return 0xe;
+ }
- return SUCCESS;
+ return FAIL;
}
+enum lit_type
+{
+ CONST_THUMB,
+ CONST_ARM,
+ CONST_VEC
+};
+
/* inst.reloc.exp describes an "=expr" load pseudo-operation.
Determine whether it can be performed with a move instruction; if
it can, convert inst.instruction to that move instruction and
inst.operands[i] describes the destination register. */
static bfd_boolean
-move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
+move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
{
unsigned long tbit;
+ bfd_boolean thumb_p = (t == CONST_THUMB);
+ bfd_boolean arm_p = (t == CONST_ARM);
+ bfd_boolean vec64_p = (t == CONST_VEC) && !inst.operands[i].issingle;
if (thumb_p)
tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
inst.error = _("invalid pseudo operation");
return TRUE;
}
- if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
+ if (inst.reloc.exp.X_op != O_constant
+ && inst.reloc.exp.X_op != O_symbol
+ && inst.reloc.exp.X_op != O_big)
{
inst.error = _("constant expression expected");
return TRUE;
}
- if (inst.reloc.exp.X_op == O_constant)
+ if ((inst.reloc.exp.X_op == O_constant
+ || inst.reloc.exp.X_op == O_big)
+ && !inst.operands[i].issingle)
+ {
+ if (thumb_p && inst.reloc.exp.X_op == O_constant)
+ {
+ if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
+ {
+ /* This can be done with a mov(1) instruction. */
+ inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
+ inst.instruction |= inst.reloc.exp.X_add_number;
+ return TRUE;
+ }
+ }
+ else if (arm_p && inst.reloc.exp.X_op == O_constant)
+ {
+ int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
+ if (value != FAIL)
+ {
+ /* This can be done with a mov instruction. */
+ inst.instruction &= LITERAL_MASK;
+ inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
+ inst.instruction |= value & 0xfff;
+ return TRUE;
+ }
+
+ value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
+ if (value != FAIL)
+ {
+ /* This can be done with a mvn instruction. */
+ inst.instruction &= LITERAL_MASK;
+ inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
+ inst.instruction |= value & 0xfff;
+ return TRUE;
+ }
+ }
+ else if (vec64_p)
+ {
+ int op = 0;
+ unsigned immbits = 0;
+ unsigned immlo = inst.operands[1].imm;
+ unsigned immhi = inst.operands[1].regisimm
+ ? inst.operands[1].reg
+ : inst.reloc.exp.X_unsigned
+ ? 0
+ : ((int64_t)((int) immlo)) >> 32;
+ int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
+ &op, 64, NT_invtype);
+
+ if (cmode == FAIL)
+ {
+ neon_invert_size (&immlo, &immhi, 64);
+ op = !op;
+ cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
+ &op, 64, NT_invtype);
+ }
+ if (cmode != FAIL)
+ {
+ inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
+ | (1 << 23)
+ | (cmode << 8)
+ | (op << 5)
+ | (1 << 4);
+ /* Fill other bits in vmov encoding for both thumb and arm. */
+ if (thumb_mode)
+ inst.instruction |= (0x7 << 29) | (0xF << 24);
+ else
+ inst.instruction |= (0xF << 28) | (0x1 << 25);
+ neon_write_immbits (immbits);
+ return TRUE;
+ }
+ }
+ }
+
+ if (add_to_lit_pool ((!inst.operands[i].isvec
+ || inst.operands[i].issingle) ? 4 : 8) == FAIL)
+ return TRUE;
+
+ inst.operands[1].reg = REG_PC;
+ inst.operands[1].isreg = 1;
+ inst.operands[1].preind = 1;
+ inst.reloc.pc_rel = 1;
+ inst.reloc.type = (thumb_p
+ ? BFD_RELOC_ARM_THUMB_OFFSET
+ : (mode_3
+ ? BFD_RELOC_ARM_HWLITERAL
+ : BFD_RELOC_ARM_LITERAL));
+ return FALSE;
+}
+
+/* inst.operands[i] was set up by parse_address. Encode it into an
+ ARM-format instruction. Reject all forms which cannot be encoded
+ into a coprocessor load/store instruction. If wb_ok is false,
+ reject use of writeback; if unind_ok is false, reject use of
+ unindexed addressing. If reloc_override is not 0, use it instead
+ of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
+ (in which case it is preserved). */
+
+static int
+encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
+{
+ if (!inst.operands[i].isreg)
+ {
+ gas_assert (inst.operands[0].isvec);
+ if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
+ return SUCCESS;
+ }
+
+ inst.instruction |= inst.operands[i].reg << 16;
+
+ gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
+
+ if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
+ {
+ gas_assert (!inst.operands[i].writeback);
+ if (!unind_ok)
+ {
+ inst.error = _("instruction does not support unindexed addressing");
+ return FAIL;
+ }
+ inst.instruction |= inst.operands[i].imm;
+ inst.instruction |= INDEX_UP;
+ return SUCCESS;
+ }
+
+ if (inst.operands[i].preind)
+ inst.instruction |= PRE_INDEX;
+
+ if (inst.operands[i].writeback)
{
- if (thumb_p)
+ if (inst.operands[i].reg == REG_PC)
{
- if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
- {
- /* This can be done with a mov(1) instruction. */
- inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
- inst.instruction |= inst.reloc.exp.X_add_number;
- return TRUE;
- }
+ inst.error = _("pc may not be used with write-back");
+ return FAIL;
}
- else
+ if (!wb_ok)
{
- int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
- if (value != FAIL)
- {
- /* This can be done with a mov instruction. */
- inst.instruction &= LITERAL_MASK;
- inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
- inst.instruction |= value & 0xfff;
- return TRUE;
- }
-
- value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
- if (value != FAIL)
- {
- /* This can be done with a mvn instruction. */
- inst.instruction &= LITERAL_MASK;
- inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
- inst.instruction |= value & 0xfff;
- return TRUE;
- }
+ inst.error = _("instruction does not support writeback");
+ return FAIL;
}
+ inst.instruction |= WRITE_BACK;
}
- if (add_to_lit_pool () == FAIL)
+ if (reloc_override)
+ inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
+ else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
+ || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
+ && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
{
- inst.error = _("literal pool insertion failed");
- return TRUE;
+ if (thumb_mode)
+ inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
+ else
+ inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
}
- inst.operands[1].reg = REG_PC;
- inst.operands[1].isreg = 1;
- inst.operands[1].preind = 1;
- inst.reloc.pc_rel = 1;
- inst.reloc.type = (thumb_p
- ? BFD_RELOC_ARM_THUMB_OFFSET
- : (mode_3
- ? BFD_RELOC_ARM_HWLITERAL
- : BFD_RELOC_ARM_LITERAL));
- return FALSE;
+
+ /* Prefer + for zero encoded value. */
+ if (!inst.operands[i].negative)
+ inst.instruction |= INDEX_UP;
+
+ return SUCCESS;
}
/* Functions for instruction encoding, sorted by sub-architecture.
{
inst.instruction |= inst.operands[0].reg << 12;
if (!inst.operands[1].isreg)
- if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
+ if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
return;
encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
check_ldr_r15_aligned ();
constraint (inst.operands[0].reg == REG_PC, BAD_PC);
inst.instruction |= inst.operands[0].reg << 12;
if (!inst.operands[1].isreg)
- if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
+ if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
return;
encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
}
{
if (opcode <= 0xffff)
inst.instruction = THUMB_OP32 (opcode);
- if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
+ if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
return;
}
if (inst.operands[1].isreg
inst.instruction = THUMB_OP16 (inst.instruction);
if (!inst.operands[1].isreg)
- if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
+ if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
return;
constraint (!inst.operands[1].preind
return FAIL;
}
-/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
- A, B, C, D. */
-
-static int
-neon_bits_same_in_bytes (unsigned imm)
-{
- return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
- && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
- && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
- && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
-}
-
-/* For immediate of above form, return 0bABCD. */
-
-static unsigned
-neon_squash_bits (unsigned imm)
-{
- return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
- | ((imm & 0x01000000) >> 21);
-}
-
-/* Compress quarter-float representation to 0b...000 abcdefgh. */
-
-static unsigned
-neon_qfloat_bits (unsigned imm)
-{
- return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
-}
-
-/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
- the instruction. *OP is passed as the initial value of the op field, and
- may be set to a different value depending on the constant (i.e.
- "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
- MVN). If the immediate looks like a repeated pattern then also
- try smaller element sizes. */
-
-static int
-neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
- unsigned *immbits, int *op, int size,
- enum neon_el_type type)
-{
- /* Only permit float immediates (including 0.0/-0.0) if the operand type is
- float. */
- if (type == NT_float && !float_p)
- return FAIL;
-
- if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
- {
- if (size != 32 || *op == 1)
- return FAIL;
- *immbits = neon_qfloat_bits (immlo);
- return 0xf;
- }
-
- if (size == 64)
- {
- if (neon_bits_same_in_bytes (immhi)
- && neon_bits_same_in_bytes (immlo))
- {
- if (*op == 1)
- return FAIL;
- *immbits = (neon_squash_bits (immhi) << 4)
- | neon_squash_bits (immlo);
- *op = 1;
- return 0xe;
- }
-
- if (immhi != immlo)
- return FAIL;
- }
-
- if (size >= 32)
- {
- if (immlo == (immlo & 0x000000ff))
- {
- *immbits = immlo;
- return 0x0;
- }
- else if (immlo == (immlo & 0x0000ff00))
- {
- *immbits = immlo >> 8;
- return 0x2;
- }
- else if (immlo == (immlo & 0x00ff0000))
- {
- *immbits = immlo >> 16;
- return 0x4;
- }
- else if (immlo == (immlo & 0xff000000))
- {
- *immbits = immlo >> 24;
- return 0x6;
- }
- else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
- {
- *immbits = (immlo >> 8) & 0xff;
- return 0xc;
- }
- else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
- {
- *immbits = (immlo >> 16) & 0xff;
- return 0xd;
- }
-
- if ((immlo & 0xffff) != (immlo >> 16))
- return FAIL;
- immlo &= 0xffff;
- }
-
- if (size >= 16)
- {
- if (immlo == (immlo & 0x000000ff))
- {
- *immbits = immlo;
- return 0x8;
- }
- else if (immlo == (immlo & 0x0000ff00))
- {
- *immbits = immlo >> 8;
- return 0xa;
- }
-
- if ((immlo & 0xff) != (immlo >> 8))
- return FAIL;
- immlo &= 0xff;
- }
-
- if (immlo == (immlo & 0x000000ff))
- {
- /* Don't allow MVN with 8-bit immediate. */
- if (*op == 1)
- return FAIL;
- *immbits = immlo;
- return 0xe;
- }
-
- return FAIL;
-}
-
-/* Write immediate bits [7:0] to the following locations:
-
- |28/24|23 19|18 16|15 4|3 0|
- | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
-
- This function is used by VMOV/VMVN/VORR/VBIC. */
-
-static void
-neon_write_immbits (unsigned immbits)
-{
- inst.instruction |= immbits & 0xf;
- inst.instruction |= ((immbits >> 4) & 0x7) << 16;
- inst.instruction |= ((immbits >> 7) & 0x1) << 24;
-}
-
-/* Invert low-order SIZE bits of XHI:XLO. */
-
-static void
-neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
-{
- unsigned immlo = xlo ? *xlo : 0;
- unsigned immhi = xhi ? *xhi : 0;
-
- switch (size)
- {
- case 8:
- immlo = (~immlo) & 0xff;
- break;
-
- case 16:
- immlo = (~immlo) & 0xffff;
- break;
-
- case 64:
- immhi = (~immhi) & 0xffffffff;
- /* fall through. */
-
- case 32:
- immlo = (~immlo) & 0xffffffff;
- break;
-
- default:
- abort ();
- }
-
- if (xlo)
- *xlo = immlo;
-
- if (xhi)
- *xhi = immhi;
-}
-
static void
do_neon_logic (void)
{
+2014-07-08 Jiong Wang <jiong.wang@arm.com>
+
+ * gas/arm/ldconst.s: Add test cases for symbol literal.
+ * gas/arm/ldconst.d: Likewise.
+ * gas/arm/vldconst.s: Add test cases for vldr.
+ * gas/arm/thumb2_vpool.s: Likewise.
+ * gas/arm/vldconst.d: New pattern for little-endian.
+ * gas/arm/thumb2_vpool.d: Likewise.
+ * gas/arm/vldconst_be.d: New pattern for big-endian.
+ * gas/arm/thumb2_vpool_be.d: Likewise.
+
+ * gas/arm/armv8-a+crypto.d: Skip for non-ELF targets.
+ * gas/arm/armv8-a+fp.d: Likewise.
+ * gas/arm/armv8-a+simd.d: Likewise.
+ * gas/arm/armv8-a-barrier-thumb.d: Likewise.
+ * gas/arm/bl-local-2.d: Likewise.
+ * gas/arm/ldgesb-bad.d: Likewise.
+ * gas/arm/ldgesh-bad.d: Likewise.
+ * gas/arm/thumb2_pool.d: Likewise.
+ * gas/arm/thumb2_pool.s: Likewise.
+
2014-06-17 Jiong Wang <jiong.wang@arm.com>
* gas/arm/armv8-a-it-bad.s: New check for deprecated sp_inc/dec within
#name: Valid v8-a+cryptov1
#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
.*: +file format .*arm.*
#name: Valid v8-a+fp
#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
.*: +file format .*arm.*
#name: Valid v8-a+simdv3
#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
.*: +file format .*arm.*
#as: -march=armv8-a -mthumb
#source: armv8-a-barrier.s
#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
.*: +file format .*arm.*
#name: bl local conversion to blx
#objdump: -drw --prefix-addresses --show-raw-insn
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
#as:
#objdump: -dr --prefix-addresses --show-raw-insn
#name: ARM ldr with immediate constant
#as: -mcpu=arm7m -EL
+# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
.*: +file format .*arm.*
0+44 <[^>]*> 43e0b0ff ? mvnmi fp, #255 ; 0xff
0+48 <[^>]*> 451fb004 ? ldrmi fp, \[pc, #-4\] ; 0+4c <[^>]*>
0+4c <[^>]*> 0000fff0 ? .*
+0+50 <[^>]*> e59f0020 ? ldr r0, \[pc, #32\] ; 0+78 <[^>]*>
+0+54 <[^>]*> e59f301c ? ldr r3, \[pc, #28\] ; 0+78 <[^>]*>
+0+58 <[^>]*> e59f8018 ? ldr r8, \[pc, #24\] ; 0+78 <[^>]*>
+0+5c <[^>]*> e59fb014 ? ldr fp, \[pc, #20\] ; 0+78 <[^>]*>
+0+60 <[^>]*> e59fe010 ? ldr lr, \[pc, #16\] ; 0+78 <[^>]*>
+0+64 <[^>]*> e59f0010 ? ldr r0, \[pc, #16\] ; 0+7c <[^>]*>
+0+68 <[^>]*> e59f300c ? ldr r3, \[pc, #12\] ; 0+7c <[^>]*>
+0+6c <[^>]*> e59f8008 ? ldr r8, \[pc, #8\] ; 0+7c <[^>]*>
+0+70 <[^>]*> e59fb004 ? ldr fp, \[pc, #4\] ; 0+7c <[^>]*>
+0+74 <[^>]*> e51fe000 ? ldr lr, \[pc, #-0\] ; 0+7c <[^>]*>
+0+78 <[^>]*> 00000000 .word 0x00000000
+ 78: R_ARM_ABS32 ext_symbol
+0+7c <[^>]*> 00001000 .word 0x00001000
+ 7c: R_ARM_ABS32 ext_symbol
ldrmi r11, =0xffffff00
ldrmi r11, =0x0000fff0
.pool
+
+ # test symbol literal support.
+ .macro ldrs const
+ .irp regindex, 0, 3, 8, 11, 14
+ ldr r\regindex, \const
+ .endr
+ .endm
+
+ ldrs "=ext_symbol"
+ ldrs "=ext_symbol + 0x1000"
+ .pool
# name: Reject ld<cc>sb instructions
# as: -march=armv7-a
# error-output: ldgesb-bad.l
+# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
# name: Reject ld<cc>sh instructions
# as: -march=armv7-a
# error-output: ldgesh-bad.l
+# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
0+00e <[^>]+> f8df 5004 ldr\.w r5, \[pc, #4\] ; 00+14 <[^>]+>
0+012 <[^>]+> 4900 ldr r1, \[pc, #0\] ; \(00+14 <[^>]+>\)
0+014 <[^>]+> 12345678 ? .word 0x12345678
+0+018 <[^>]+> 4907 ldr r1, \[pc, #28\] ; \(00000038 <[^>]+>\)
+0+01a <[^>]+> 4c07 ldr r4, \[pc, #28\] ; \(00000038 <[^>]+>\)
+0+01c <[^>]+> f8df 9018 ldr.w r9, \[pc, #24\] ; 00000038 <[^>]+>
+0+020 <[^>]+> f8df c014 ldr.w ip, \[pc, #20\] ; 00000038 <[^>]+>
+0+024 <[^>]+> f8df d010 ldr.w sp, \[pc, #16\] ; 00000038 <[^>]+>
+0+028 <[^>]+> 4904 ldr r1, \[pc, #16\] ; \(0000003c <[^>]+>\)
+0+02a <[^>]+> 4c04 ldr r4, \[pc, #16\] ; \(0000003c <[^>]+>\)
+0+02c <[^>]+> f8df 900c ldr.w r9, \[pc, #12\] ; 0000003c <[^>]+>
+0+030 <[^>]+> f8df c008 ldr.w ip, \[pc, #8\] ; 0000003c <[^>]+>
+0+034 <[^>]+> f8df d004 ldr.w sp, \[pc, #4\] ; 0000003c <[^>]+>
+0+038 <[^>]+> 00000000 .word 0x00000000
+ 38: R_ARM_ABS32 ext_symbol
+0+03c <[^>]+> 00001000 .word 0x00001000
+ 3c: R_ARM_ABS32 ext_symbol
+
ldr.w r5, =0x12345678
ldr r1, =0x12345678
.pool
+
+ # test symbol literal support.
+ .macro ldrs const
+ .irp regindex, 1, 4, 9, 12, 13
+ ldr r\regindex, \const
+ .endr
+ .endm
+
+ ldrs "=ext_symbol"
+ ldrs "=ext_symbol + 0x1000"
+ .pool
--- /dev/null
+# as: -march=armv6t2 -EL
+# objdump: -dr --prefix-addresses --show-raw-insn
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#name: Thumb2 vldr with immediate constant
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+00000000 <thumb2_ldr> ed9f 0a0f vldr s0, \[pc, #60\] ; 00000040 <thumb2_ldr\+0x40>
+00000004 <thumb2_ldr\+0x4> ed9f 7a0e vldr s14, \[pc, #56\] ; 00000040 <thumb2_ldr\+0x40>
+00000008 <thumb2_ldr\+0x8> ed9f ea0d vldr s28, \[pc, #52\] ; 00000040 <thumb2_ldr\+0x40>
+0000000c <thumb2_ldr\+0xc> eddf fa0c vldr s31, \[pc, #48\] ; 00000040 <thumb2_ldr\+0x40>
+00000010 <thumb2_ldr\+0x10> ed9f 0a0c vldr s0, \[pc, #48\] ; 00000044 <thumb2_ldr\+0x44>
+00000014 <thumb2_ldr\+0x14> ed9f 7a0b vldr s14, \[pc, #44\] ; 00000044 <thumb2_ldr\+0x44>
+00000018 <thumb2_ldr\+0x18> ed9f ea0a vldr s28, \[pc, #40\] ; 00000044 <thumb2_ldr\+0x44>
+0000001c <thumb2_ldr\+0x1c> eddf fa09 vldr s31, \[pc, #36\] ; 00000044 <thumb2_ldr\+0x44>
+00000020 <thumb2_ldr\+0x20> ed9f 0a09 vldr s0, \[pc, #36\] ; 00000048 <thumb2_ldr\+0x48>
+00000024 <thumb2_ldr\+0x24> ed9f 7a08 vldr s14, \[pc, #32\] ; 00000048 <thumb2_ldr\+0x48>
+00000028 <thumb2_ldr\+0x28> ed9f ea07 vldr s28, \[pc, #28\] ; 00000048 <thumb2_ldr\+0x48>
+0000002c <thumb2_ldr\+0x2c> eddf fa06 vldr s31, \[pc, #24\] ; 00000048 <thumb2_ldr\+0x48>
+00000030 <thumb2_ldr\+0x30> ed9f 0a06 vldr s0, \[pc, #24\] ; 0000004c <thumb2_ldr\+0x4c>
+00000034 <thumb2_ldr\+0x34> ed9f 7a05 vldr s14, \[pc, #20\] ; 0000004c <thumb2_ldr\+0x4c>
+00000038 <thumb2_ldr\+0x38> ed9f ea04 vldr s28, \[pc, #16\] ; 0000004c <thumb2_ldr\+0x4c>
+0000003c <thumb2_ldr\+0x3c> eddf fa03 vldr s31, \[pc, #12\] ; 0000004c <thumb2_ldr\+0x4c>
+00000040 <thumb2_ldr\+0x40> 00000000 .word 0x00000000
+00000044 <thumb2_ldr\+0x44> ff000000 .word 0xff000000
+00000048 <thumb2_ldr\+0x48> ffffffff .word 0xffffffff
+0000004c <thumb2_ldr\+0x4c> 0fff0000 .word 0x0fff0000
+00000050 <thumb2_ldr\+0x50> ed9f 0a0f vldr s0, \[pc, #60\] ; 00000090 <thumb2_ldr\+0x90>
+00000054 <thumb2_ldr\+0x54> ed9f 7a0e vldr s14, \[pc, #56\] ; 00000090 <thumb2_ldr\+0x90>
+00000058 <thumb2_ldr\+0x58> ed9f ea0d vldr s28, \[pc, #52\] ; 00000090 <thumb2_ldr\+0x90>
+0000005c <thumb2_ldr\+0x5c> eddf fa0c vldr s31, \[pc, #48\] ; 00000090 <thumb2_ldr\+0x90>
+00000060 <thumb2_ldr\+0x60> ed9f 0a0c vldr s0, \[pc, #48\] ; 00000094 <thumb2_ldr\+0x94>
+00000064 <thumb2_ldr\+0x64> ed9f 7a0b vldr s14, \[pc, #44\] ; 00000094 <thumb2_ldr\+0x94>
+00000068 <thumb2_ldr\+0x68> ed9f ea0a vldr s28, \[pc, #40\] ; 00000094 <thumb2_ldr\+0x94>
+0000006c <thumb2_ldr\+0x6c> eddf fa09 vldr s31, \[pc, #36\] ; 00000094 <thumb2_ldr\+0x94>
+00000070 <thumb2_ldr\+0x70> ed9f 0a09 vldr s0, \[pc, #36\] ; 00000098 <thumb2_ldr\+0x98>
+00000074 <thumb2_ldr\+0x74> ed9f 7a08 vldr s14, \[pc, #32\] ; 00000098 <thumb2_ldr\+0x98>
+00000078 <thumb2_ldr\+0x78> ed9f ea07 vldr s28, \[pc, #28\] ; 00000098 <thumb2_ldr\+0x98>
+0000007c <thumb2_ldr\+0x7c> eddf fa06 vldr s31, \[pc, #24\] ; 00000098 <thumb2_ldr\+0x98>
+00000080 <thumb2_ldr\+0x80> ed9f 0a06 vldr s0, \[pc, #24\] ; 0000009c <thumb2_ldr\+0x9c>
+00000084 <thumb2_ldr\+0x84> ed9f 7a05 vldr s14, \[pc, #20\] ; 0000009c <thumb2_ldr\+0x9c>
+00000088 <thumb2_ldr\+0x88> ed9f ea04 vldr s28, \[pc, #16\] ; 0000009c <thumb2_ldr\+0x9c>
+0000008c <thumb2_ldr\+0x8c> eddf fa03 vldr s31, \[pc, #12\] ; 0000009c <thumb2_ldr\+0x9c>
+00000090 <thumb2_ldr\+0x90> 00000000 .word 0x00000000
+00000094 <thumb2_ldr\+0x94> 00ff0000 .word 0x00ff0000
+00000098 <thumb2_ldr\+0x98> ff00ffff .word 0xff00ffff
+0000009c <thumb2_ldr\+0x9c> 00fff000 .word 0x00fff000
+000000a0 <thumb2_ldr\+0xa0> ef80 0e30 vmov.i64 d0, #0x0000000000000000
+000000a4 <thumb2_ldr\+0xa4> ef80 ee30 vmov.i64 d14, #0x0000000000000000
+000000a8 <thumb2_ldr\+0xa8> efc0 ce30 vmov.i64 d28, #0x0000000000000000
+000000ac <thumb2_ldr\+0xac> efc0 fe30 vmov.i64 d31, #0x0000000000000000
+000000b0 <thumb2_ldr\+0xb0> ed9f 0b0b vldr d0, \[pc, #44\] ; 000000e0 <thumb2_ldr\+0xe0>
+000000b4 <thumb2_ldr\+0xb4> ed9f eb0a vldr d14, \[pc, #40\] ; 000000e0 <thumb2_ldr\+0xe0>
+000000b8 <thumb2_ldr\+0xb8> eddf cb09 vldr d28, \[pc, #36\] ; 000000e0 <thumb2_ldr\+0xe0>
+000000bc <thumb2_ldr\+0xbc> eddf fb08 vldr d31, \[pc, #32\] ; 000000e0 <thumb2_ldr\+0xe0>
+000000c0 <thumb2_ldr\+0xc0> ff87 0e3f vmov.i64 d0, #0xffffffffffffffff
+000000c4 <thumb2_ldr\+0xc4> ff87 ee3f vmov.i64 d14, #0xffffffffffffffff
+000000c8 <thumb2_ldr\+0xc8> ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff
+000000cc <thumb2_ldr\+0xcc> ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff
+000000d0 <thumb2_ldr\+0xd0> ed9f 0b05 vldr d0, \[pc, #20\] ; 000000e8 <thumb2_ldr\+0xe8>
+000000d4 <thumb2_ldr\+0xd4> ed9f eb04 vldr d14, \[pc, #16\] ; 000000e8 <thumb2_ldr\+0xe8>
+000000d8 <thumb2_ldr\+0xd8> eddf cb03 vldr d28, \[pc, #12\] ; 000000e8 <thumb2_ldr\+0xe8>
+000000dc <thumb2_ldr\+0xdc> eddf fb02 vldr d31, \[pc, #8\] ; 000000e8 <thumb2_ldr\+0xe8>
+000000e0 <thumb2_ldr\+0xe0> ca000000 .word 0xca000000
+000000e4 <thumb2_ldr\+0xe4> 00000000 .word 0x00000000
+000000e8 <thumb2_ldr\+0xe8> 0fff0000 .word 0x0fff0000
+000000ec <thumb2_ldr\+0xec> 00000000 .word 0x00000000
+000000f0 <thumb2_ldr\+0xf0> ef80 0e30 vmov.i64 d0, #0x0000000000000000
+000000f4 <thumb2_ldr\+0xf4> ef80 ee30 vmov.i64 d14, #0x0000000000000000
+000000f8 <thumb2_ldr\+0xf8> efc0 ce30 vmov.i64 d28, #0x0000000000000000
+000000fc <thumb2_ldr\+0xfc> efc0 fe30 vmov.i64 d31, #0x0000000000000000
+00000100 <thumb2_ldr\+0x100> ef80 0e34 vmov.i64 d0, #0x0000000000ff0000
+00000104 <thumb2_ldr\+0x104> ef80 ee34 vmov.i64 d14, #0x0000000000ff0000
+00000108 <thumb2_ldr\+0x108> efc0 ce34 vmov.i64 d28, #0x0000000000ff0000
+0000010c <thumb2_ldr\+0x10c> efc0 fe34 vmov.i64 d31, #0x0000000000ff0000
+00000110 <thumb2_ldr\+0x110> ef80 0e39 vmov.i64 d0, #0x00000000ff0000ff
+00000114 <thumb2_ldr\+0x114> ef80 ee39 vmov.i64 d14, #0x00000000ff0000ff
+00000118 <thumb2_ldr\+0x118> efc0 ce39 vmov.i64 d28, #0x00000000ff0000ff
+0000011c <thumb2_ldr\+0x11c> efc0 fe39 vmov.i64 d31, #0x00000000ff0000ff
+00000120 <thumb2_ldr\+0x120> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000130 <thumb2_ldr\+0x130>
+00000124 <thumb2_ldr\+0x124> ed9f eb02 vldr d14, \[pc, #8\] ; 00000130 <thumb2_ldr\+0x130>
+00000128 <thumb2_ldr\+0x128> eddf cb01 vldr d28, \[pc, #4\] ; 00000130 <thumb2_ldr\+0x130>
+0000012c <thumb2_ldr\+0x12c> eddf fb00 vldr d31, \[pc\] ; 00000130 <thumb2_ldr\+0x130>
+00000130 <thumb2_ldr\+0x130> 00fff000 .word 0x00fff000
+00000134 <thumb2_ldr\+0x134> 00000000 .word 0x00000000
+00000138 <thumb2_ldr\+0x138> ef80 0e30 vmov.i64 d0, #0x0000000000000000
+0000013c <thumb2_ldr\+0x13c> ef80 ee30 vmov.i64 d14, #0x0000000000000000
+00000140 <thumb2_ldr\+0x140> efc0 ce30 vmov.i64 d28, #0x0000000000000000
+00000144 <thumb2_ldr\+0x144> efc0 fe30 vmov.i64 d31, #0x0000000000000000
+00000148 <thumb2_ldr\+0x148> ff80 0e30 vmov.i64 d0, #0xff00000000000000
+0000014c <thumb2_ldr\+0x14c> ff80 ee30 vmov.i64 d14, #0xff00000000000000
+00000150 <thumb2_ldr\+0x150> ffc0 ce30 vmov.i64 d28, #0xff00000000000000
+00000154 <thumb2_ldr\+0x154> ffc0 fe30 vmov.i64 d31, #0xff00000000000000
+00000158 <thumb2_ldr\+0x158> ff87 0e3f vmov.i64 d0, #0xffffffffffffffff
+0000015c <thumb2_ldr\+0x15c> ff87 ee3f vmov.i64 d14, #0xffffffffffffffff
+00000160 <thumb2_ldr\+0x160> ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff
+00000164 <thumb2_ldr\+0x164> ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff
+00000168 <thumb2_ldr\+0x168> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000178 <thumb2_ldr\+0x178>
+0000016c <thumb2_ldr\+0x16c> ed9f eb02 vldr d14, \[pc, #8\] ; 00000178 <thumb2_ldr\+0x178>
+00000170 <thumb2_ldr\+0x170> eddf cb01 vldr d28, \[pc, #4\] ; 00000178 <thumb2_ldr\+0x178>
+00000174 <thumb2_ldr\+0x174> eddf fb00 vldr d31, \[pc\] ; 00000178 <thumb2_ldr\+0x178>
+00000178 <thumb2_ldr\+0x178> 00000000 .word 0x00000000
+0000017c <thumb2_ldr\+0x17c> 0fff0000 .word 0x0fff0000
+00000180 <thumb2_ldr\+0x180> ef80 0e30 vmov.i64 d0, #0x0000000000000000
+00000184 <thumb2_ldr\+0x184> ef80 ee30 vmov.i64 d14, #0x0000000000000000
+00000188 <thumb2_ldr\+0x188> efc0 ce30 vmov.i64 d28, #0x0000000000000000
+0000018c <thumb2_ldr\+0x18c> efc0 fe30 vmov.i64 d31, #0x0000000000000000
+00000190 <thumb2_ldr\+0x190> ed9f 0b0b vldr d0, \[pc, #44\] ; 000001c0 <thumb2_ldr\+0x1c0>
+00000194 <thumb2_ldr\+0x194> ed9f eb0a vldr d14, \[pc, #40\] ; 000001c0 <thumb2_ldr\+0x1c0>
+00000198 <thumb2_ldr\+0x198> eddf cb09 vldr d28, \[pc, #36\] ; 000001c0 <thumb2_ldr\+0x1c0>
+0000019c <thumb2_ldr\+0x19c> eddf fb08 vldr d31, \[pc, #32\] ; 000001c0 <thumb2_ldr\+0x1c0>
+000001a0 <thumb2_ldr\+0x1a0> ed9f 0b09 vldr d0, \[pc, #36\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001a4 <thumb2_ldr\+0x1a4> ed9f eb08 vldr d14, \[pc, #32\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001a8 <thumb2_ldr\+0x1a8> eddf cb07 vldr d28, \[pc, #28\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001ac <thumb2_ldr\+0x1ac> eddf fb06 vldr d31, \[pc, #24\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001b0 <thumb2_ldr\+0x1b0> ed9f 0b05 vldr d0, \[pc, #20\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001b4 <thumb2_ldr\+0x1b4> ed9f eb04 vldr d14, \[pc, #16\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001b8 <thumb2_ldr\+0x1b8> eddf cb03 vldr d28, \[pc, #12\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001bc <thumb2_ldr\+0x1bc> eddf fb02 vldr d31, \[pc, #8\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001c0 <thumb2_ldr\+0x1c0> 00000000 .word 0x00000000
+000001c4 <thumb2_ldr\+0x1c4> 000ff000 .word 0x000ff000
+000001c8 <thumb2_ldr\+0x1c8> f0000000 .word 0xf0000000
+000001cc <thumb2_ldr\+0x1cc> 0ff00fff .word 0x0ff00fff
+000001d0 <thumb2_ldr\+0x1d0> ed9f 1b01 vldr d1, \[pc, #4\] ; 000001d8 <thumb2_ldr\+0x1d8>
+ \.\.\.
+000001dc <thumb2_ldr\+0x1dc> 0000fff0 .word 0x0000fff0
+000001e0 <thumb2_ldr\+0x1e0> f101 0000 add.w r0, r1, #0
+000001e4 <thumb2_ldr\+0x1e4> ed9f 1b00 vldr d1, \[pc\] ; 000001e8 <thumb2_ldr\+0x1e8>
+000001e8 <thumb2_ldr\+0x1e8> 00000000 .word 0x00000000
+000001ec <thumb2_ldr\+0x1ec> 0000fff0 .word 0x0000fff0
+000001f0 <thumb2_ldr\+0x1f0> ed9f 1b11 vldr d1, \[pc, #68\] ; 00000238 <thumb2_ldr\+0x238>
+000001f4 <thumb2_ldr\+0x1f4> ed9f 1a12 vldr s2, \[pc, #72\] ; 00000240 <thumb2_ldr\+0x240>
+000001f8 <thumb2_ldr\+0x1f8> ed9f 3b13 vldr d3, \[pc, #76\] ; 00000248 <thumb2_ldr\+0x248>
+000001fc <thumb2_ldr\+0x1fc> ed9f 2a11 vldr s4, \[pc, #68\] ; 00000244 <thumb2_ldr\+0x244>
+00000200 <thumb2_ldr\+0x200> ed9f 5b11 vldr d5, \[pc, #68\] ; 00000248 <thumb2_ldr\+0x248>
+00000204 <thumb2_ldr\+0x204> ed9f 6b12 vldr d6, \[pc, #72\] ; 00000250 <thumb2_ldr\+0x250>
+00000208 <thumb2_ldr\+0x208> ed9f 7b13 vldr d7, \[pc, #76\] ; 00000258 <thumb2_ldr\+0x258>
+0000020c <thumb2_ldr\+0x20c> ed9f 4a14 vldr s8, \[pc, #80\] ; 00000260 <thumb2_ldr\+0x260>
+00000210 <thumb2_ldr\+0x210> ed9f 9b15 vldr d9, \[pc, #84\] ; 00000268 <thumb2_ldr\+0x268>
+00000214 <thumb2_ldr\+0x214> ed9f 5a13 vldr s10, \[pc, #76\] ; 00000264 <thumb2_ldr\+0x264>
+00000218 <thumb2_ldr\+0x218> ed9f bb15 vldr d11, \[pc, #84\] ; 00000270 <thumb2_ldr\+0x270>
+0000021c <thumb2_ldr\+0x21c> ed9f 6a16 vldr s12, \[pc, #88\] ; 00000278 <thumb2_ldr\+0x278>
+00000220 <thumb2_ldr\+0x220> eddf 6a16 vldr s13, \[pc, #88\] ; 0000027c <thumb2_ldr\+0x27c>
+00000224 <thumb2_ldr\+0x224> ed9f 7a07 vldr s14, \[pc, #28\] ; 00000244 <thumb2_ldr\+0x244>
+00000228 <thumb2_ldr\+0x228> eddf 7a04 vldr s15, \[pc, #16\] ; 0000023c <thumb2_ldr\+0x23c>
+0000022c <thumb2_ldr\+0x22c> eddf 0b12 vldr d16, \[pc, #72\] ; 00000278 <thumb2_ldr\+0x278>
+00000230 <thumb2_ldr\+0x230> eddf 1b13 vldr d17, \[pc, #76\] ; 00000280 <thumb2_ldr\+0x280>
+ \.\.\.
+0000023c <thumb2_ldr\+0x23c> 0000fff0 .word 0x0000fff0
+00000240 <thumb2_ldr\+0x240> ff000000 .word 0xff000000
+00000244 <thumb2_ldr\+0x244> ff000001 .word 0xff000001
+00000248 <thumb2_ldr\+0x248> 00000001 .word 0x00000001
+0000024c <thumb2_ldr\+0x24c> 0000fff0 .word 0x0000fff0
+00000250 <thumb2_ldr\+0x250> 00000002 .word 0x00000002
+00000254 <thumb2_ldr\+0x254> 0000fff0 .word 0x0000fff0
+00000258 <thumb2_ldr\+0x258> 00000003 .word 0x00000003
+0000025c <thumb2_ldr\+0x25c> 0000fff0 .word 0x0000fff0
+00000260 <thumb2_ldr\+0x260> ff000002 .word 0xff000002
+00000264 <thumb2_ldr\+0x264> ff000003 .word 0xff000003
+00000268 <thumb2_ldr\+0x268> 00000004 .word 0x00000004
+0000026c <thumb2_ldr\+0x26c> 0000fff0 .word 0x0000fff0
+00000270 <thumb2_ldr\+0x270> 00000005 .word 0x00000005
+00000274 <thumb2_ldr\+0x274> 0000fff0 .word 0x0000fff0
+00000278 <thumb2_ldr\+0x278> ff000004 .word 0xff000004
+0000027c <thumb2_ldr\+0x27c> ff000005 .word 0xff000005
+00000280 <thumb2_ldr\+0x280> 0000fff0 .word 0x0000fff0
+00000284 <thumb2_ldr\+0x284> ff000004 .word 0xff000004
--- /dev/null
+ .text
+ .fpu neon
+ .thumb
+ .syntax unified
+ .thumb_func
+thumb2_ldr:
+ .macro vlxr regtype const
+ .irp regindex, 0, 14, 28, 31
+ vldr \regtype\regindex, \const
+ .endr
+ .endm
+ # Thumb-2 support vldr literal pool also.
+ vlxr s "=0"
+ vlxr s "=0xff000000"
+ vlxr s "=-1"
+ vlxr s "=0x0fff0000"
+ .pool
+
+ vlxr s "=0"
+ vlxr s "=0x00ff0000"
+ vlxr s "=0xff00ffff"
+ vlxr s "=0x00fff000"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0xca000000"
+ vlxr d "=-1"
+ vlxr d "=0x0fff0000"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0x00ff0000"
+ vlxr d "=0xff0000ff"
+ vlxr d "=0x00fff000"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0xff00000000000000"
+ vlxr d "=-1"
+ vlxr d "=0x0fff000000000000"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0x00ff00000000000"
+ vlxr d "=0xff00ffff0000000"
+ vlxr d "=0xff00ffff0000000"
+ .pool
+
+ # pool should be aligned to 8-byte.
+ .p2align 3
+ vldr d1, =0x0000fff000000000
+ .pool
+
+ # no error when code is align already.
+ .p2align 3
+ add r0, r1, #0
+ vldr d1, =0x0000fff000000000
+ .pool
+
+ .p2align 3
+ vldr d1, =0x0000fff000000000
+ vldr s2, =0xff000000
+ # padding A
+ vldr d3, =0x0000fff000000001
+ # reuse padding slot A
+ vldr s4, =0xff000001
+ # reuse d3
+ vldr d5, =0x0000fff000000001
+ # new 8-byte entry
+ vldr d6, =0x0000fff000000002
+ # new 8-byte entry
+ vldr d7, =0x0000fff000000003
+ # new 4-byte entry
+ vldr s8, =0xff000002
+ # padding B
+ vldr d9, =0x0000fff000000004
+ # reuse padding slot B
+ vldr s10, =0xff000003
+ # new 8-byte entry
+ vldr d11, =0x0000fff000000005
+ # new 4 entry
+ vldr s12, =0xff000004
+ # new 4 entry
+ vldr s13, =0xff000005
+ # reuse value of s4 in pool
+ vldr s14, =0xff000001
+ # reuse high part of d1 in pool
+ vldr s15, =0x0000fff0
+ # 8-byte entry reuse two 4-byte entries.
+ # d16 reuse s12, s13
+ vldr d16, =0xff000005ff000004
+ # d17 should not reuse high part of d11 and s12.
+ # because the it's align 8-byte aligned.
+ vldr d17, =0xff0000040000fff0
+ .pool
--- /dev/null
+# as: -march=armv6t2 -mbig-endian
+# objdump: -dr --prefix-addresses --show-raw-insn
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#name: Thumb2 vldr with immediate constant
+#source: thumb2_vpool.s
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+00000000 <thumb2_ldr> ed9f 0a0f vldr s0, \[pc, #60\] ; 00000040 <thumb2_ldr\+0x40>
+00000004 <thumb2_ldr\+0x4> ed9f 7a0e vldr s14, \[pc, #56\] ; 00000040 <thumb2_ldr\+0x40>
+00000008 <thumb2_ldr\+0x8> ed9f ea0d vldr s28, \[pc, #52\] ; 00000040 <thumb2_ldr\+0x40>
+0000000c <thumb2_ldr\+0xc> eddf fa0c vldr s31, \[pc, #48\] ; 00000040 <thumb2_ldr\+0x40>
+00000010 <thumb2_ldr\+0x10> ed9f 0a0c vldr s0, \[pc, #48\] ; 00000044 <thumb2_ldr\+0x44>
+00000014 <thumb2_ldr\+0x14> ed9f 7a0b vldr s14, \[pc, #44\] ; 00000044 <thumb2_ldr\+0x44>
+00000018 <thumb2_ldr\+0x18> ed9f ea0a vldr s28, \[pc, #40\] ; 00000044 <thumb2_ldr\+0x44>
+0000001c <thumb2_ldr\+0x1c> eddf fa09 vldr s31, \[pc, #36\] ; 00000044 <thumb2_ldr\+0x44>
+00000020 <thumb2_ldr\+0x20> ed9f 0a09 vldr s0, \[pc, #36\] ; 00000048 <thumb2_ldr\+0x48>
+00000024 <thumb2_ldr\+0x24> ed9f 7a08 vldr s14, \[pc, #32\] ; 00000048 <thumb2_ldr\+0x48>
+00000028 <thumb2_ldr\+0x28> ed9f ea07 vldr s28, \[pc, #28\] ; 00000048 <thumb2_ldr\+0x48>
+0000002c <thumb2_ldr\+0x2c> eddf fa06 vldr s31, \[pc, #24\] ; 00000048 <thumb2_ldr\+0x48>
+00000030 <thumb2_ldr\+0x30> ed9f 0a06 vldr s0, \[pc, #24\] ; 0000004c <thumb2_ldr\+0x4c>
+00000034 <thumb2_ldr\+0x34> ed9f 7a05 vldr s14, \[pc, #20\] ; 0000004c <thumb2_ldr\+0x4c>
+00000038 <thumb2_ldr\+0x38> ed9f ea04 vldr s28, \[pc, #16\] ; 0000004c <thumb2_ldr\+0x4c>
+0000003c <thumb2_ldr\+0x3c> eddf fa03 vldr s31, \[pc, #12\] ; 0000004c <thumb2_ldr\+0x4c>
+00000040 <thumb2_ldr\+0x40> 00000000 .word 0x00000000
+00000044 <thumb2_ldr\+0x44> ff000000 .word 0xff000000
+00000048 <thumb2_ldr\+0x48> ffffffff .word 0xffffffff
+0000004c <thumb2_ldr\+0x4c> 0fff0000 .word 0x0fff0000
+00000050 <thumb2_ldr\+0x50> ed9f 0a0f vldr s0, \[pc, #60\] ; 00000090 <thumb2_ldr\+0x90>
+00000054 <thumb2_ldr\+0x54> ed9f 7a0e vldr s14, \[pc, #56\] ; 00000090 <thumb2_ldr\+0x90>
+00000058 <thumb2_ldr\+0x58> ed9f ea0d vldr s28, \[pc, #52\] ; 00000090 <thumb2_ldr\+0x90>
+0000005c <thumb2_ldr\+0x5c> eddf fa0c vldr s31, \[pc, #48\] ; 00000090 <thumb2_ldr\+0x90>
+00000060 <thumb2_ldr\+0x60> ed9f 0a0c vldr s0, \[pc, #48\] ; 00000094 <thumb2_ldr\+0x94>
+00000064 <thumb2_ldr\+0x64> ed9f 7a0b vldr s14, \[pc, #44\] ; 00000094 <thumb2_ldr\+0x94>
+00000068 <thumb2_ldr\+0x68> ed9f ea0a vldr s28, \[pc, #40\] ; 00000094 <thumb2_ldr\+0x94>
+0000006c <thumb2_ldr\+0x6c> eddf fa09 vldr s31, \[pc, #36\] ; 00000094 <thumb2_ldr\+0x94>
+00000070 <thumb2_ldr\+0x70> ed9f 0a09 vldr s0, \[pc, #36\] ; 00000098 <thumb2_ldr\+0x98>
+00000074 <thumb2_ldr\+0x74> ed9f 7a08 vldr s14, \[pc, #32\] ; 00000098 <thumb2_ldr\+0x98>
+00000078 <thumb2_ldr\+0x78> ed9f ea07 vldr s28, \[pc, #28\] ; 00000098 <thumb2_ldr\+0x98>
+0000007c <thumb2_ldr\+0x7c> eddf fa06 vldr s31, \[pc, #24\] ; 00000098 <thumb2_ldr\+0x98>
+00000080 <thumb2_ldr\+0x80> ed9f 0a06 vldr s0, \[pc, #24\] ; 0000009c <thumb2_ldr\+0x9c>
+00000084 <thumb2_ldr\+0x84> ed9f 7a05 vldr s14, \[pc, #20\] ; 0000009c <thumb2_ldr\+0x9c>
+00000088 <thumb2_ldr\+0x88> ed9f ea04 vldr s28, \[pc, #16\] ; 0000009c <thumb2_ldr\+0x9c>
+0000008c <thumb2_ldr\+0x8c> eddf fa03 vldr s31, \[pc, #12\] ; 0000009c <thumb2_ldr\+0x9c>
+00000090 <thumb2_ldr\+0x90> 00000000 .word 0x00000000
+00000094 <thumb2_ldr\+0x94> 00ff0000 .word 0x00ff0000
+00000098 <thumb2_ldr\+0x98> ff00ffff .word 0xff00ffff
+0000009c <thumb2_ldr\+0x9c> 00fff000 .word 0x00fff000
+000000a0 <thumb2_ldr\+0xa0> ef80 0e30 vmov.i64 d0, #0x0000000000000000
+000000a4 <thumb2_ldr\+0xa4> ef80 ee30 vmov.i64 d14, #0x0000000000000000
+000000a8 <thumb2_ldr\+0xa8> efc0 ce30 vmov.i64 d28, #0x0000000000000000
+000000ac <thumb2_ldr\+0xac> efc0 fe30 vmov.i64 d31, #0x0000000000000000
+000000b0 <thumb2_ldr\+0xb0> ed9f 0b0b vldr d0, \[pc, #44\] ; 000000e0 <thumb2_ldr\+0xe0>
+000000b4 <thumb2_ldr\+0xb4> ed9f eb0a vldr d14, \[pc, #40\] ; 000000e0 <thumb2_ldr\+0xe0>
+000000b8 <thumb2_ldr\+0xb8> eddf cb09 vldr d28, \[pc, #36\] ; 000000e0 <thumb2_ldr\+0xe0>
+000000bc <thumb2_ldr\+0xbc> eddf fb08 vldr d31, \[pc, #32\] ; 000000e0 <thumb2_ldr\+0xe0>
+000000c0 <thumb2_ldr\+0xc0> ff87 0e3f vmov.i64 d0, #0xffffffffffffffff
+000000c4 <thumb2_ldr\+0xc4> ff87 ee3f vmov.i64 d14, #0xffffffffffffffff
+000000c8 <thumb2_ldr\+0xc8> ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff
+000000cc <thumb2_ldr\+0xcc> ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff
+000000d0 <thumb2_ldr\+0xd0> ed9f 0b05 vldr d0, \[pc, #20\] ; 000000e8 <thumb2_ldr\+0xe8>
+000000d4 <thumb2_ldr\+0xd4> ed9f eb04 vldr d14, \[pc, #16\] ; 000000e8 <thumb2_ldr\+0xe8>
+000000d8 <thumb2_ldr\+0xd8> eddf cb03 vldr d28, \[pc, #12\] ; 000000e8 <thumb2_ldr\+0xe8>
+000000dc <thumb2_ldr\+0xdc> eddf fb02 vldr d31, \[pc, #8\] ; 000000e8 <thumb2_ldr\+0xe8>
+000000e0 <thumb2_ldr\+0xe0> 00000000 .word 0x00000000
+000000e4 <thumb2_ldr\+0xe4> ca000000 .word 0xca000000
+000000e8 <thumb2_ldr\+0xe8> 00000000 .word 0x00000000
+000000ec <thumb2_ldr\+0xec> 0fff0000 .word 0x0fff0000
+000000f0 <thumb2_ldr\+0xf0> ef80 0e30 vmov.i64 d0, #0x0000000000000000
+000000f4 <thumb2_ldr\+0xf4> ef80 ee30 vmov.i64 d14, #0x0000000000000000
+000000f8 <thumb2_ldr\+0xf8> efc0 ce30 vmov.i64 d28, #0x0000000000000000
+000000fc <thumb2_ldr\+0xfc> efc0 fe30 vmov.i64 d31, #0x0000000000000000
+00000100 <thumb2_ldr\+0x100> ef80 0e34 vmov.i64 d0, #0x0000000000ff0000
+00000104 <thumb2_ldr\+0x104> ef80 ee34 vmov.i64 d14, #0x0000000000ff0000
+00000108 <thumb2_ldr\+0x108> efc0 ce34 vmov.i64 d28, #0x0000000000ff0000
+0000010c <thumb2_ldr\+0x10c> efc0 fe34 vmov.i64 d31, #0x0000000000ff0000
+00000110 <thumb2_ldr\+0x110> ef80 0e39 vmov.i64 d0, #0x00000000ff0000ff
+00000114 <thumb2_ldr\+0x114> ef80 ee39 vmov.i64 d14, #0x00000000ff0000ff
+00000118 <thumb2_ldr\+0x118> efc0 ce39 vmov.i64 d28, #0x00000000ff0000ff
+0000011c <thumb2_ldr\+0x11c> efc0 fe39 vmov.i64 d31, #0x00000000ff0000ff
+00000120 <thumb2_ldr\+0x120> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000130 <thumb2_ldr\+0x130>
+00000124 <thumb2_ldr\+0x124> ed9f eb02 vldr d14, \[pc, #8\] ; 00000130 <thumb2_ldr\+0x130>
+00000128 <thumb2_ldr\+0x128> eddf cb01 vldr d28, \[pc, #4\] ; 00000130 <thumb2_ldr\+0x130>
+0000012c <thumb2_ldr\+0x12c> eddf fb00 vldr d31, \[pc\] ; 00000130 <thumb2_ldr\+0x130>
+00000130 <thumb2_ldr\+0x130> 00000000 .word 0x00000000
+00000134 <thumb2_ldr\+0x134> 00fff000 .word 0x00fff000
+00000138 <thumb2_ldr\+0x138> ef80 0e30 vmov.i64 d0, #0x0000000000000000
+0000013c <thumb2_ldr\+0x13c> ef80 ee30 vmov.i64 d14, #0x0000000000000000
+00000140 <thumb2_ldr\+0x140> efc0 ce30 vmov.i64 d28, #0x0000000000000000
+00000144 <thumb2_ldr\+0x144> efc0 fe30 vmov.i64 d31, #0x0000000000000000
+00000148 <thumb2_ldr\+0x148> ff80 0e30 vmov.i64 d0, #0xff00000000000000
+0000014c <thumb2_ldr\+0x14c> ff80 ee30 vmov.i64 d14, #0xff00000000000000
+00000150 <thumb2_ldr\+0x150> ffc0 ce30 vmov.i64 d28, #0xff00000000000000
+00000154 <thumb2_ldr\+0x154> ffc0 fe30 vmov.i64 d31, #0xff00000000000000
+00000158 <thumb2_ldr\+0x158> ff87 0e3f vmov.i64 d0, #0xffffffffffffffff
+0000015c <thumb2_ldr\+0x15c> ff87 ee3f vmov.i64 d14, #0xffffffffffffffff
+00000160 <thumb2_ldr\+0x160> ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff
+00000164 <thumb2_ldr\+0x164> ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff
+00000168 <thumb2_ldr\+0x168> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000178 <thumb2_ldr\+0x178>
+0000016c <thumb2_ldr\+0x16c> ed9f eb02 vldr d14, \[pc, #8\] ; 00000178 <thumb2_ldr\+0x178>
+00000170 <thumb2_ldr\+0x170> eddf cb01 vldr d28, \[pc, #4\] ; 00000178 <thumb2_ldr\+0x178>
+00000174 <thumb2_ldr\+0x174> eddf fb00 vldr d31, \[pc\] ; 00000178 <thumb2_ldr\+0x178>
+00000178 <thumb2_ldr\+0x178> 0fff0000 .word 0x0fff0000
+0000017c <thumb2_ldr\+0x17c> 00000000 .word 0x00000000
+00000180 <thumb2_ldr\+0x180> ef80 0e30 vmov.i64 d0, #0x0000000000000000
+00000184 <thumb2_ldr\+0x184> ef80 ee30 vmov.i64 d14, #0x0000000000000000
+00000188 <thumb2_ldr\+0x188> efc0 ce30 vmov.i64 d28, #0x0000000000000000
+0000018c <thumb2_ldr\+0x18c> efc0 fe30 vmov.i64 d31, #0x0000000000000000
+00000190 <thumb2_ldr\+0x190> ed9f 0b0b vldr d0, \[pc, #44\] ; 000001c0 <thumb2_ldr\+0x1c0>
+00000194 <thumb2_ldr\+0x194> ed9f eb0a vldr d14, \[pc, #40\] ; 000001c0 <thumb2_ldr\+0x1c0>
+00000198 <thumb2_ldr\+0x198> eddf cb09 vldr d28, \[pc, #36\] ; 000001c0 <thumb2_ldr\+0x1c0>
+0000019c <thumb2_ldr\+0x19c> eddf fb08 vldr d31, \[pc, #32\] ; 000001c0 <thumb2_ldr\+0x1c0>
+000001a0 <thumb2_ldr\+0x1a0> ed9f 0b09 vldr d0, \[pc, #36\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001a4 <thumb2_ldr\+0x1a4> ed9f eb08 vldr d14, \[pc, #32\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001a8 <thumb2_ldr\+0x1a8> eddf cb07 vldr d28, \[pc, #28\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001ac <thumb2_ldr\+0x1ac> eddf fb06 vldr d31, \[pc, #24\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001b0 <thumb2_ldr\+0x1b0> ed9f 0b05 vldr d0, \[pc, #20\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001b4 <thumb2_ldr\+0x1b4> ed9f eb04 vldr d14, \[pc, #16\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001b8 <thumb2_ldr\+0x1b8> eddf cb03 vldr d28, \[pc, #12\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001bc <thumb2_ldr\+0x1bc> eddf fb02 vldr d31, \[pc, #8\] ; 000001c8 <thumb2_ldr\+0x1c8>
+000001c0 <thumb2_ldr\+0x1c0> 000ff000 .word 0x000ff000
+000001c4 <thumb2_ldr\+0x1c4> 00000000 .word 0x00000000
+000001c8 <thumb2_ldr\+0x1c8> 0ff00fff .word 0x0ff00fff
+000001cc <thumb2_ldr\+0x1cc> f0000000 .word 0xf0000000
+000001d0 <thumb2_ldr\+0x1d0> ed9f 1b01 vldr d1, \[pc, #4\] ; 000001d8 <thumb2_ldr\+0x1d8>
+000001d4 <thumb2_ldr\+0x1d4> 0000 movs r0, r0
+000001d6 <thumb2_ldr\+0x1d6> 0000 movs r0, r0
+000001d8 <thumb2_ldr\+0x1d8> 0000fff0 .word 0x0000fff0
+000001dc <thumb2_ldr\+0x1dc> 00000000 .word 0x00000000
+000001e0 <thumb2_ldr\+0x1e0> f101 0000 add.w r0, r1, #0
+000001e4 <thumb2_ldr\+0x1e4> ed9f 1b00 vldr d1, \[pc\] ; 000001e8 <thumb2_ldr\+0x1e8>
+000001e8 <thumb2_ldr\+0x1e8> 0000fff0 .word 0x0000fff0
+000001ec <thumb2_ldr\+0x1ec> 00000000 .word 0x00000000
+000001f0 <thumb2_ldr\+0x1f0> ed9f 1b11 vldr d1, \[pc, #68\] ; 00000238 <thumb2_ldr\+0x238>
+000001f4 <thumb2_ldr\+0x1f4> ed9f 1a12 vldr s2, \[pc, #72\] ; 00000240 <thumb2_ldr\+0x240>
+000001f8 <thumb2_ldr\+0x1f8> ed9f 3b13 vldr d3, \[pc, #76\] ; 00000248 <thumb2_ldr\+0x248>
+000001fc <thumb2_ldr\+0x1fc> ed9f 2a11 vldr s4, \[pc, #68\] ; 00000244 <thumb2_ldr\+0x244>
+00000200 <thumb2_ldr\+0x200> ed9f 5b11 vldr d5, \[pc, #68\] ; 00000248 <thumb2_ldr\+0x248>
+00000204 <thumb2_ldr\+0x204> ed9f 6b12 vldr d6, \[pc, #72\] ; 00000250 <thumb2_ldr\+0x250>
+00000208 <thumb2_ldr\+0x208> ed9f 7b13 vldr d7, \[pc, #76\] ; 00000258 <thumb2_ldr\+0x258>
+0000020c <thumb2_ldr\+0x20c> ed9f 4a14 vldr s8, \[pc, #80\] ; 00000260 <thumb2_ldr\+0x260>
+00000210 <thumb2_ldr\+0x210> ed9f 9b15 vldr d9, \[pc, #84\] ; 00000268 <thumb2_ldr\+0x268>
+00000214 <thumb2_ldr\+0x214> ed9f 5a13 vldr s10, \[pc, #76\] ; 00000264 <thumb2_ldr\+0x264>
+00000218 <thumb2_ldr\+0x218> ed9f bb15 vldr d11, \[pc, #84\] ; 00000270 <thumb2_ldr\+0x270>
+0000021c <thumb2_ldr\+0x21c> ed9f 6a16 vldr s12, \[pc, #88\] ; 00000278 <thumb2_ldr\+0x278>
+00000220 <thumb2_ldr\+0x220> eddf 6a16 vldr s13, \[pc, #88\] ; 0000027c <thumb2_ldr\+0x27c>
+00000224 <thumb2_ldr\+0x224> ed9f 7a07 vldr s14, \[pc, #28\] ; 00000244 <thumb2_ldr\+0x244>
+00000228 <thumb2_ldr\+0x228> eddf 7a03 vldr s15, \[pc, #12\] ; 00000238 <thumb2_ldr\+0x238>
+0000022c <thumb2_ldr\+0x22c> eddf 0b14 vldr d16, \[pc, #80\] ; 00000280 <thumb2_ldr\+0x280>
+00000230 <thumb2_ldr\+0x230> eddf 1b15 vldr d17, \[pc, #84\] ; 00000288 <thumb2_ldr\+0x288>
+00000234 <thumb2_ldr\+0x234> 0000 movs r0, r0
+00000236 <thumb2_ldr\+0x236> 0000 movs r0, r0
+00000238 <thumb2_ldr\+0x238> 0000fff0 .word 0x0000fff0
+0000023c <thumb2_ldr\+0x23c> 00000000 .word 0x00000000
+00000240 <thumb2_ldr\+0x240> ff000000 .word 0xff000000
+00000244 <thumb2_ldr\+0x244> ff000001 .word 0xff000001
+00000248 <thumb2_ldr\+0x248> 0000fff0 .word 0x0000fff0
+0000024c <thumb2_ldr\+0x24c> 00000001 .word 0x00000001
+00000250 <thumb2_ldr\+0x250> 0000fff0 .word 0x0000fff0
+00000254 <thumb2_ldr\+0x254> 00000002 .word 0x00000002
+00000258 <thumb2_ldr\+0x258> 0000fff0 .word 0x0000fff0
+0000025c <thumb2_ldr\+0x25c> 00000003 .word 0x00000003
+00000260 <thumb2_ldr\+0x260> ff000002 .word 0xff000002
+00000264 <thumb2_ldr\+0x264> ff000003 .word 0xff000003
+00000268 <thumb2_ldr\+0x268> 0000fff0 .word 0x0000fff0
+0000026c <thumb2_ldr\+0x26c> 00000004 .word 0x00000004
+00000270 <thumb2_ldr\+0x270> 0000fff0 .word 0x0000fff0
+00000274 <thumb2_ldr\+0x274> 00000005 .word 0x00000005
+00000278 <thumb2_ldr\+0x278> ff000004 .word 0xff000004
+0000027c <thumb2_ldr\+0x27c> ff000005 .word 0xff000005
+00000280 <thumb2_ldr\+0x280> ff000005 .word 0xff000005
+00000284 <thumb2_ldr\+0x284> ff000004 .word 0xff000004
+00000288 <thumb2_ldr\+0x288> ff000004 .word 0xff000004
+0000028c <thumb2_ldr\+0x28c> 0000fff0 .word 0x0000fff0
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: ARM vldr with immediate constant
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
+#as: -mcpu=arm7m -EL
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+00000000 <foo> ed9f0a0e vldr s0, \[pc, #56\] ; 00000040 <foo\+0x40>
+00000004 <foo\+0x4> ed9f7a0d vldr s14, \[pc, #52\] ; 00000040 <foo\+0x40>
+00000008 <foo\+0x8> ed9fea0c vldr s28, \[pc, #48\] ; 00000040 <foo\+0x40>
+0000000c <foo\+0xc> eddffa0b vldr s31, \[pc, #44\] ; 00000040 <foo\+0x40>
+00000010 <foo\+0x10> ed9f0a0b vldr s0, \[pc, #44\] ; 00000044 <foo\+0x44>
+00000014 <foo\+0x14> ed9f7a0a vldr s14, \[pc, #40\] ; 00000044 <foo\+0x44>
+00000018 <foo\+0x18> ed9fea09 vldr s28, \[pc, #36\] ; 00000044 <foo\+0x44>
+0000001c <foo\+0x1c> eddffa08 vldr s31, \[pc, #32\] ; 00000044 <foo\+0x44>
+00000020 <foo\+0x20> ed9f0a08 vldr s0, \[pc, #32\] ; 00000048 <foo\+0x48>
+00000024 <foo\+0x24> ed9f7a07 vldr s14, \[pc, #28\] ; 00000048 <foo\+0x48>
+00000028 <foo\+0x28> ed9fea06 vldr s28, \[pc, #24\] ; 00000048 <foo\+0x48>
+0000002c <foo\+0x2c> eddffa05 vldr s31, \[pc, #20\] ; 00000048 <foo\+0x48>
+00000030 <foo\+0x30> ed9f0a05 vldr s0, \[pc, #20\] ; 0000004c <foo\+0x4c>
+00000034 <foo\+0x34> ed9f7a04 vldr s14, \[pc, #16\] ; 0000004c <foo\+0x4c>
+00000038 <foo\+0x38> ed9fea03 vldr s28, \[pc, #12\] ; 0000004c <foo\+0x4c>
+0000003c <foo\+0x3c> eddffa02 vldr s31, \[pc, #8\] ; 0000004c <foo\+0x4c>
+00000040 <foo\+0x40> 00000000 .word 0x00000000
+00000044 <foo\+0x44> ff000000 .word 0xff000000
+00000048 <foo\+0x48> ffffffff .word 0xffffffff
+0000004c <foo\+0x4c> 0fff0000 .word 0x0fff0000
+00000050 <foo\+0x50> ed9f0a0e vldr s0, \[pc, #56\] ; 00000090 <foo\+0x90>
+00000054 <foo\+0x54> ed9f7a0d vldr s14, \[pc, #52\] ; 00000090 <foo\+0x90>
+00000058 <foo\+0x58> ed9fea0c vldr s28, \[pc, #48\] ; 00000090 <foo\+0x90>
+0000005c <foo\+0x5c> eddffa0b vldr s31, \[pc, #44\] ; 00000090 <foo\+0x90>
+00000060 <foo\+0x60> ed9f0a0b vldr s0, \[pc, #44\] ; 00000094 <foo\+0x94>
+00000064 <foo\+0x64> ed9f7a0a vldr s14, \[pc, #40\] ; 00000094 <foo\+0x94>
+00000068 <foo\+0x68> ed9fea09 vldr s28, \[pc, #36\] ; 00000094 <foo\+0x94>
+0000006c <foo\+0x6c> eddffa08 vldr s31, \[pc, #32\] ; 00000094 <foo\+0x94>
+00000070 <foo\+0x70> ed9f0a08 vldr s0, \[pc, #32\] ; 00000098 <foo\+0x98>
+00000074 <foo\+0x74> ed9f7a07 vldr s14, \[pc, #28\] ; 00000098 <foo\+0x98>
+00000078 <foo\+0x78> ed9fea06 vldr s28, \[pc, #24\] ; 00000098 <foo\+0x98>
+0000007c <foo\+0x7c> eddffa05 vldr s31, \[pc, #20\] ; 00000098 <foo\+0x98>
+00000080 <foo\+0x80> ed9f0a05 vldr s0, \[pc, #20\] ; 0000009c <foo\+0x9c>
+00000084 <foo\+0x84> ed9f7a04 vldr s14, \[pc, #16\] ; 0000009c <foo\+0x9c>
+00000088 <foo\+0x88> ed9fea03 vldr s28, \[pc, #12\] ; 0000009c <foo\+0x9c>
+0000008c <foo\+0x8c> eddffa02 vldr s31, \[pc, #8\] ; 0000009c <foo\+0x9c>
+00000090 <foo\+0x90> 00000000 .word 0x00000000
+00000094 <foo\+0x94> 00ff0000 .word 0x00ff0000
+00000098 <foo\+0x98> ff00ffff .word 0xff00ffff
+0000009c <foo\+0x9c> 00fff000 .word 0x00fff000
+000000a0 <foo\+0xa0> 0d9f0a0e vldreq s0, \[pc, #56\] ; 000000e0 <foo\+0xe0>
+000000a4 <foo\+0xa4> 0d9f7a0d vldreq s14, \[pc, #52\] ; 000000e0 <foo\+0xe0>
+000000a8 <foo\+0xa8> 0d9fea0c vldreq s28, \[pc, #48\] ; 000000e0 <foo\+0xe0>
+000000ac <foo\+0xac> 0ddffa0b vldreq s31, \[pc, #44\] ; 000000e0 <foo\+0xe0>
+000000b0 <foo\+0xb0> 0d9f0a0b vldreq s0, \[pc, #44\] ; 000000e4 <foo\+0xe4>
+000000b4 <foo\+0xb4> 0d9f7a0a vldreq s14, \[pc, #40\] ; 000000e4 <foo\+0xe4>
+000000b8 <foo\+0xb8> 0d9fea09 vldreq s28, \[pc, #36\] ; 000000e4 <foo\+0xe4>
+000000bc <foo\+0xbc> 0ddffa08 vldreq s31, \[pc, #32\] ; 000000e4 <foo\+0xe4>
+000000c0 <foo\+0xc0> 0d9f0a08 vldreq s0, \[pc, #32\] ; 000000e8 <foo\+0xe8>
+000000c4 <foo\+0xc4> 0d9f7a07 vldreq s14, \[pc, #28\] ; 000000e8 <foo\+0xe8>
+000000c8 <foo\+0xc8> 0d9fea06 vldreq s28, \[pc, #24\] ; 000000e8 <foo\+0xe8>
+000000cc <foo\+0xcc> 0ddffa05 vldreq s31, \[pc, #20\] ; 000000e8 <foo\+0xe8>
+000000d0 <foo\+0xd0> 0d9f0a05 vldreq s0, \[pc, #20\] ; 000000ec <foo\+0xec>
+000000d4 <foo\+0xd4> 0d9f7a04 vldreq s14, \[pc, #16\] ; 000000ec <foo\+0xec>
+000000d8 <foo\+0xd8> 0d9fea03 vldreq s28, \[pc, #12\] ; 000000ec <foo\+0xec>
+000000dc <foo\+0xdc> 0ddffa02 vldreq s31, \[pc, #8\] ; 000000ec <foo\+0xec>
+000000e0 <foo\+0xe0> 00000000 .word 0x00000000
+000000e4 <foo\+0xe4> 0000ff00 .word 0x0000ff00
+000000e8 <foo\+0xe8> ffff00ff .word 0xffff00ff
+000000ec <foo\+0xec> 000fff00 .word 0x000fff00
+000000f0 <foo\+0xf0> 4d9f0a0e vldrmi s0, \[pc, #56\] ; 00000130 <foo\+0x130>
+000000f4 <foo\+0xf4> 4d9f7a0d vldrmi s14, \[pc, #52\] ; 00000130 <foo\+0x130>
+000000f8 <foo\+0xf8> 4d9fea0c vldrmi s28, \[pc, #48\] ; 00000130 <foo\+0x130>
+000000fc <foo\+0xfc> 4ddffa0b vldrmi s31, \[pc, #44\] ; 00000130 <foo\+0x130>
+00000100 <foo\+0x100> 4d9f0a0b vldrmi s0, \[pc, #44\] ; 00000134 <foo\+0x134>
+00000104 <foo\+0x104> 4d9f7a0a vldrmi s14, \[pc, #40\] ; 00000134 <foo\+0x134>
+00000108 <foo\+0x108> 4d9fea09 vldrmi s28, \[pc, #36\] ; 00000134 <foo\+0x134>
+0000010c <foo\+0x10c> 4ddffa08 vldrmi s31, \[pc, #32\] ; 00000134 <foo\+0x134>
+00000110 <foo\+0x110> 4d9f0a08 vldrmi s0, \[pc, #32\] ; 00000138 <foo\+0x138>
+00000114 <foo\+0x114> 4d9f7a07 vldrmi s14, \[pc, #28\] ; 00000138 <foo\+0x138>
+00000118 <foo\+0x118> 4d9fea06 vldrmi s28, \[pc, #24\] ; 00000138 <foo\+0x138>
+0000011c <foo\+0x11c> 4ddffa05 vldrmi s31, \[pc, #20\] ; 00000138 <foo\+0x138>
+00000120 <foo\+0x120> 4d9f0a05 vldrmi s0, \[pc, #20\] ; 0000013c <foo\+0x13c>
+00000124 <foo\+0x124> 4d9f7a04 vldrmi s14, \[pc, #16\] ; 0000013c <foo\+0x13c>
+00000128 <foo\+0x128> 4d9fea03 vldrmi s28, \[pc, #12\] ; 0000013c <foo\+0x13c>
+0000012c <foo\+0x12c> 4ddffa02 vldrmi s31, \[pc, #8\] ; 0000013c <foo\+0x13c>
+00000130 <foo\+0x130> 00000000 .word 0x00000000
+00000134 <foo\+0x134> 000000ff .word 0x000000ff
+00000138 <foo\+0x138> ffffff00 .word 0xffffff00
+0000013c <foo\+0x13c> 0000fff0 .word 0x0000fff0
+00000140 <foo\+0x140> f2800e30 vmov.i64 d0, #0x0000000000000000
+00000144 <foo\+0x144> f280ee30 vmov.i64 d14, #0x0000000000000000
+00000148 <foo\+0x148> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+0000014c <foo\+0x14c> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+00000150 <foo\+0x150> ed9f0b0a vldr d0, \[pc, #40\] ; 00000180 <foo\+0x180>
+00000154 <foo\+0x154> ed9feb09 vldr d14, \[pc, #36\] ; 00000180 <foo\+0x180>
+00000158 <foo\+0x158> eddfcb08 vldr d28, \[pc, #32\] ; 00000180 <foo\+0x180>
+0000015c <foo\+0x15c> eddffb07 vldr d31, \[pc, #28\] ; 00000180 <foo\+0x180>
+00000160 <foo\+0x160> f3870e3f vmov.i64 d0, #0xffffffffffffffff
+00000164 <foo\+0x164> f387ee3f vmov.i64 d14, #0xffffffffffffffff
+00000168 <foo\+0x168> f3c7ce3f vmov.i64 d28, #0xffffffffffffffff
+0000016c <foo\+0x16c> f3c7fe3f vmov.i64 d31, #0xffffffffffffffff
+00000170 <foo\+0x170> ed9f0b04 vldr d0, \[pc, #16\] ; 00000188 <foo\+0x188>
+00000174 <foo\+0x174> ed9feb03 vldr d14, \[pc, #12\] ; 00000188 <foo\+0x188>
+00000178 <foo\+0x178> eddfcb02 vldr d28, \[pc, #8\] ; 00000188 <foo\+0x188>
+0000017c <foo\+0x17c> eddffb01 vldr d31, \[pc, #4\] ; 00000188 <foo\+0x188>
+00000180 <foo\+0x180> ca000000 .word 0xca000000
+00000184 <foo\+0x184> 00000000 .word 0x00000000
+00000188 <foo\+0x188> 0fff0000 .word 0x0fff0000
+0000018c <foo\+0x18c> 00000000 .word 0x00000000
+00000190 <foo\+0x190> f2800e30 vmov.i64 d0, #0x0000000000000000
+00000194 <foo\+0x194> f280ee30 vmov.i64 d14, #0x0000000000000000
+00000198 <foo\+0x198> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+0000019c <foo\+0x19c> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+000001a0 <foo\+0x1a0> f2800e34 vmov.i64 d0, #0x0000000000ff0000
+000001a4 <foo\+0x1a4> f280ee34 vmov.i64 d14, #0x0000000000ff0000
+000001a8 <foo\+0x1a8> f2c0ce34 vmov.i64 d28, #0x0000000000ff0000
+000001ac <foo\+0x1ac> f2c0fe34 vmov.i64 d31, #0x0000000000ff0000
+000001b0 <foo\+0x1b0> f2800e39 vmov.i64 d0, #0x00000000ff0000ff
+000001b4 <foo\+0x1b4> f280ee39 vmov.i64 d14, #0x00000000ff0000ff
+000001b8 <foo\+0x1b8> f2c0ce39 vmov.i64 d28, #0x00000000ff0000ff
+000001bc <foo\+0x1bc> f2c0fe39 vmov.i64 d31, #0x00000000ff0000ff
+000001c0 <foo\+0x1c0> ed9f0b02 vldr d0, \[pc, #8\] ; 000001d0 <foo\+0x1d0>
+000001c4 <foo\+0x1c4> ed9feb01 vldr d14, \[pc, #4\] ; 000001d0 <foo\+0x1d0>
+000001c8 <foo\+0x1c8> eddfcb00 vldr d28, \[pc\] ; 000001d0 <foo\+0x1d0>
+000001cc <foo\+0x1cc> ed5ffb01 vldr d31, \[pc, #-4\] ; 000001d0 <foo\+0x1d0>
+000001d0 <foo\+0x1d0> 00fff000 .word 0x00fff000
+000001d4 <foo\+0x1d4> 00000000 .word 0x00000000
+000001d8 <foo\+0x1d8> f2800e30 vmov.i64 d0, #0x0000000000000000
+000001dc <foo\+0x1dc> f280ee30 vmov.i64 d14, #0x0000000000000000
+000001e0 <foo\+0x1e0> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+000001e4 <foo\+0x1e4> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+000001e8 <foo\+0x1e8> f2800e32 vmov.i64 d0, #0x000000000000ff00
+000001ec <foo\+0x1ec> f280ee32 vmov.i64 d14, #0x000000000000ff00
+000001f0 <foo\+0x1f0> f2c0ce32 vmov.i64 d28, #0x000000000000ff00
+000001f4 <foo\+0x1f4> f2c0fe32 vmov.i64 d31, #0x000000000000ff00
+000001f8 <foo\+0x1f8> f2800e3d vmov.i64 d0, #0x00000000ffff00ff
+000001fc <foo\+0x1fc> f280ee3d vmov.i64 d14, #0x00000000ffff00ff
+00000200 <foo\+0x200> f2c0ce3d vmov.i64 d28, #0x00000000ffff00ff
+00000204 <foo\+0x204> f2c0fe3d vmov.i64 d31, #0x00000000ffff00ff
+00000208 <foo\+0x208> 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000218 <foo\+0x218>
+0000020c <foo\+0x20c> 0d9feb01 vldreq d14, \[pc, #4\] ; 00000218 <foo\+0x218>
+00000210 <foo\+0x210> 0ddfcb00 vldreq d28, \[pc\] ; 00000218 <foo\+0x218>
+00000214 <foo\+0x214> 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000218 <foo\+0x218>
+00000218 <foo\+0x218> 000fff00 .word 0x000fff00
+0000021c <foo\+0x21c> 00000000 .word 0x00000000
+00000220 <foo\+0x220> f2800e30 vmov.i64 d0, #0x0000000000000000
+00000224 <foo\+0x224> f280ee30 vmov.i64 d14, #0x0000000000000000
+00000228 <foo\+0x228> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+0000022c <foo\+0x22c> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+00000230 <foo\+0x230> f2800e31 vmov.i64 d0, #0x00000000000000ff
+00000234 <foo\+0x234> f280ee31 vmov.i64 d14, #0x00000000000000ff
+00000238 <foo\+0x238> f2c0ce31 vmov.i64 d28, #0x00000000000000ff
+0000023c <foo\+0x23c> f2c0fe31 vmov.i64 d31, #0x00000000000000ff
+00000240 <foo\+0x240> f2800e3e vmov.i64 d0, #0x00000000ffffff00
+00000244 <foo\+0x244> f280ee3e vmov.i64 d14, #0x00000000ffffff00
+00000248 <foo\+0x248> f2c0ce3e vmov.i64 d28, #0x00000000ffffff00
+0000024c <foo\+0x24c> f2c0fe3e vmov.i64 d31, #0x00000000ffffff00
+00000250 <foo\+0x250> f2800e33 vmov.i64 d0, #0x000000000000ffff
+00000254 <foo\+0x254> f280ee33 vmov.i64 d14, #0x000000000000ffff
+00000258 <foo\+0x258> f2c0ce33 vmov.i64 d28, #0x000000000000ffff
+0000025c <foo\+0x25c> f2c0fe33 vmov.i64 d31, #0x000000000000ffff
+00000260 <foo\+0x260> f2800e30 vmov.i64 d0, #0x0000000000000000
+00000264 <foo\+0x264> f280ee30 vmov.i64 d14, #0x0000000000000000
+00000268 <foo\+0x268> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+0000026c <foo\+0x26c> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+00000270 <foo\+0x270> f3800e30 vmov.i64 d0, #0xff00000000000000
+00000274 <foo\+0x274> f380ee30 vmov.i64 d14, #0xff00000000000000
+00000278 <foo\+0x278> f3c0ce30 vmov.i64 d28, #0xff00000000000000
+0000027c <foo\+0x27c> f3c0fe30 vmov.i64 d31, #0xff00000000000000
+00000280 <foo\+0x280> f3870e3f vmov.i64 d0, #0xffffffffffffffff
+00000284 <foo\+0x284> f387ee3f vmov.i64 d14, #0xffffffffffffffff
+00000288 <foo\+0x288> f3c7ce3f vmov.i64 d28, #0xffffffffffffffff
+0000028c <foo\+0x28c> f3c7fe3f vmov.i64 d31, #0xffffffffffffffff
+00000290 <foo\+0x290> ed9f0b02 vldr d0, \[pc, #8\] ; 000002a0 <foo\+0x2a0>
+00000294 <foo\+0x294> ed9feb01 vldr d14, \[pc, #4\] ; 000002a0 <foo\+0x2a0>
+00000298 <foo\+0x298> eddfcb00 vldr d28, \[pc\] ; 000002a0 <foo\+0x2a0>
+0000029c <foo\+0x29c> ed5ffb01 vldr d31, \[pc, #-4\] ; 000002a0 <foo\+0x2a0>
+000002a0 <foo\+0x2a0> 00000000 .word 0x00000000
+000002a4 <foo\+0x2a4> 0fff0000 .word 0x0fff0000
+000002a8 <foo\+0x2a8> f2800e30 vmov.i64 d0, #0x0000000000000000
+000002ac <foo\+0x2ac> f280ee30 vmov.i64 d14, #0x0000000000000000
+000002b0 <foo\+0x2b0> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+000002b4 <foo\+0x2b4> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+000002b8 <foo\+0x2b8> ed9f0b0a vldr d0, \[pc, #40\] ; 000002e8 <foo\+0x2e8>
+000002bc <foo\+0x2bc> ed9feb09 vldr d14, \[pc, #36\] ; 000002e8 <foo\+0x2e8>
+000002c0 <foo\+0x2c0> eddfcb08 vldr d28, \[pc, #32\] ; 000002e8 <foo\+0x2e8>
+000002c4 <foo\+0x2c4> eddffb07 vldr d31, \[pc, #28\] ; 000002e8 <foo\+0x2e8>
+000002c8 <foo\+0x2c8> ed9f0b08 vldr d0, \[pc, #32\] ; 000002f0 <foo\+0x2f0>
+000002cc <foo\+0x2cc> ed9feb07 vldr d14, \[pc, #28\] ; 000002f0 <foo\+0x2f0>
+000002d0 <foo\+0x2d0> eddfcb06 vldr d28, \[pc, #24\] ; 000002f0 <foo\+0x2f0>
+000002d4 <foo\+0x2d4> eddffb05 vldr d31, \[pc, #20\] ; 000002f0 <foo\+0x2f0>
+000002d8 <foo\+0x2d8> ed9f0b06 vldr d0, \[pc, #24\] ; 000002f8 <foo\+0x2f8>
+000002dc <foo\+0x2dc> ed9feb05 vldr d14, \[pc, #20\] ; 000002f8 <foo\+0x2f8>
+000002e0 <foo\+0x2e0> eddfcb04 vldr d28, \[pc, #16\] ; 000002f8 <foo\+0x2f8>
+000002e4 <foo\+0x2e4> eddffb03 vldr d31, \[pc, #12\] ; 000002f8 <foo\+0x2f8>
+000002e8 <foo\+0x2e8> 00000000 .word 0x00000000
+000002ec <foo\+0x2ec> 000ff000 .word 0x000ff000
+000002f0 <foo\+0x2f0> f0000000 .word 0xf0000000
+000002f4 <foo\+0x2f4> 0ff00fff .word 0x0ff00fff
+000002f8 <foo\+0x2f8> 00000000 .word 0x00000000
+000002fc <foo\+0x2fc> 000fff00 .word 0x000fff00
+00000300 <foo\+0x300> f2800e30 vmov.i64 d0, #0x0000000000000000
+00000304 <foo\+0x304> f280ee30 vmov.i64 d14, #0x0000000000000000
+00000308 <foo\+0x308> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+0000030c <foo\+0x30c> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+00000310 <foo\+0x310> f2820e30 vmov.i64 d0, #0x0000ff0000000000
+00000314 <foo\+0x314> f282ee30 vmov.i64 d14, #0x0000ff0000000000
+00000318 <foo\+0x318> f2c2ce30 vmov.i64 d28, #0x0000ff0000000000
+0000031c <foo\+0x31c> f2c2fe30 vmov.i64 d31, #0x0000ff0000000000
+00000320 <foo\+0x320> f3850e30 vmov.i64 d0, #0xffff00ff00000000
+00000324 <foo\+0x324> f385ee30 vmov.i64 d14, #0xffff00ff00000000
+00000328 <foo\+0x328> f3c5ce30 vmov.i64 d28, #0xffff00ff00000000
+0000032c <foo\+0x32c> f3c5fe30 vmov.i64 d31, #0xffff00ff00000000
+00000330 <foo\+0x330> 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000340 <foo\+0x340>
+00000334 <foo\+0x334> 0d9feb01 vldreq d14, \[pc, #4\] ; 00000340 <foo\+0x340>
+00000338 <foo\+0x338> 0ddfcb00 vldreq d28, \[pc\] ; 00000340 <foo\+0x340>
+0000033c <foo\+0x33c> 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000340 <foo\+0x340>
+00000340 <foo\+0x340> 00000000 .word 0x00000000
+00000344 <foo\+0x344> 000fff00 .word 0x000fff00
+00000348 <foo\+0x348> f2800e30 vmov.i64 d0, #0x0000000000000000
+0000034c <foo\+0x34c> f280ee30 vmov.i64 d14, #0x0000000000000000
+00000350 <foo\+0x350> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+00000354 <foo\+0x354> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+00000358 <foo\+0x358> f2810e30 vmov.i64 d0, #0x000000ff00000000
+0000035c <foo\+0x35c> f281ee30 vmov.i64 d14, #0x000000ff00000000
+00000360 <foo\+0x360> f2c1ce30 vmov.i64 d28, #0x000000ff00000000
+00000364 <foo\+0x364> f2c1fe30 vmov.i64 d31, #0x000000ff00000000
+00000368 <foo\+0x368> f3860e30 vmov.i64 d0, #0xffffff0000000000
+0000036c <foo\+0x36c> f386ee30 vmov.i64 d14, #0xffffff0000000000
+00000370 <foo\+0x370> f3c6ce30 vmov.i64 d28, #0xffffff0000000000
+00000374 <foo\+0x374> f3c6fe30 vmov.i64 d31, #0xffffff0000000000
+00000378 <foo\+0x378> 4d9f0b02 vldrmi d0, \[pc, #8\] ; 00000388 <foo\+0x388>
+0000037c <foo\+0x37c> 4d9feb01 vldrmi d14, \[pc, #4\] ; 00000388 <foo\+0x388>
+00000380 <foo\+0x380> 4ddfcb00 vldrmi d28, \[pc\] ; 00000388 <foo\+0x388>
+00000384 <foo\+0x384> 4d5ffb01 vldrmi d31, \[pc, #-4\] ; 00000388 <foo\+0x388>
+00000388 <foo\+0x388> 00000000 .word 0x00000000
+0000038c <foo\+0x38c> 0000fff0 .word 0x0000fff0
+00000390 <foo\+0x390> ed9f1b00 vldr d1, \[pc\] ; 00000398 <foo\+0x398>
+ \.\.\.
+0000039c <foo\+0x39c> 0000fff0 .word 0x0000fff0
+000003a0 <foo\+0x3a0> e2810000 add r0, r1, #0
+000003a4 <foo\+0x3a4> ed1f1b01 vldr d1, \[pc, #-4\] ; 000003a8 <foo\+0x3a8>
+000003a8 <foo\+0x3a8> 00000000 .word 0x00000000
+000003ac <foo\+0x3ac> 0000fff0 .word 0x0000fff0
+000003b0 <foo\+0x3b0> ed9f1b10 vldr d1, \[pc, #64\] ; 000003f8 <foo\+0x3f8>
+000003b4 <foo\+0x3b4> ed9f1a11 vldr s2, \[pc, #68\] ; 00000400 <foo\+0x400>
+000003b8 <foo\+0x3b8> ed9f3b12 vldr d3, \[pc, #72\] ; 00000408 <foo\+0x408>
+000003bc <foo\+0x3bc> ed9f2a10 vldr s4, \[pc, #64\] ; 00000404 <foo\+0x404>
+000003c0 <foo\+0x3c0> ed9f5b10 vldr d5, \[pc, #64\] ; 00000408 <foo\+0x408>
+000003c4 <foo\+0x3c4> ed9f6b11 vldr d6, \[pc, #68\] ; 00000410 <foo\+0x410>
+000003c8 <foo\+0x3c8> ed9f7b12 vldr d7, \[pc, #72\] ; 00000418 <foo\+0x418>
+000003cc <foo\+0x3cc> ed9f4a13 vldr s8, \[pc, #76\] ; 00000420 <foo\+0x420>
+000003d0 <foo\+0x3d0> ed9f9b14 vldr d9, \[pc, #80\] ; 00000428 <foo\+0x428>
+000003d4 <foo\+0x3d4> ed9f5a12 vldr s10, \[pc, #72\] ; 00000424 <foo\+0x424>
+000003d8 <foo\+0x3d8> ed9fbb14 vldr d11, \[pc, #80\] ; 00000430 <foo\+0x430>
+000003dc <foo\+0x3dc> ed9f6a15 vldr s12, \[pc, #84\] ; 00000438 <foo\+0x438>
+000003e0 <foo\+0x3e0> eddf6a15 vldr s13, \[pc, #84\] ; 0000043c <foo\+0x43c>
+000003e4 <foo\+0x3e4> ed9f7a06 vldr s14, \[pc, #24\] ; 00000404 <foo\+0x404>
+000003e8 <foo\+0x3e8> eddf7a03 vldr s15, \[pc, #12\] ; 000003fc <foo\+0x3fc>
+000003ec <foo\+0x3ec> eddf0b11 vldr d16, \[pc, #68\] ; 00000438 <foo\+0x438>
+000003f0 <foo\+0x3f0> eddf1b12 vldr d17, \[pc, #72\] ; 00000440 <foo\+0x440>
+ \.\.\.
+000003fc <foo\+0x3fc> 0000fff0 .word 0x0000fff0
+00000400 <foo\+0x400> ff000000 .word 0xff000000
+00000404 <foo\+0x404> ff000001 .word 0xff000001
+00000408 <foo\+0x408> 00000001 .word 0x00000001
+0000040c <foo\+0x40c> 0000fff0 .word 0x0000fff0
+00000410 <foo\+0x410> 00000002 .word 0x00000002
+00000414 <foo\+0x414> 0000fff0 .word 0x0000fff0
+00000418 <foo\+0x418> 00000003 .word 0x00000003
+0000041c <foo\+0x41c> 0000fff0 .word 0x0000fff0
+00000420 <foo\+0x420> ff000002 .word 0xff000002
+00000424 <foo\+0x424> ff000003 .word 0xff000003
+00000428 <foo\+0x428> 00000004 .word 0x00000004
+0000042c <foo\+0x42c> 0000fff0 .word 0x0000fff0
+00000430 <foo\+0x430> 00000005 .word 0x00000005
+00000434 <foo\+0x434> 0000fff0 .word 0x0000fff0
+00000438 <foo\+0x438> ff000004 .word 0xff000004
+0000043c <foo\+0x43c> ff000005 .word 0xff000005
+00000440 <foo\+0x440> 0000fff0 .word 0x0000fff0
+00000444 <foo\+0x444> ff000004 .word 0xff000004
--- /dev/null
+@ Test file for ARM/GAS -- vldr reg, =... expressions.
+.fpu neon
+.text
+.align
+foo:
+ # test both low and high index of the
+ # Advanced SIMD and Floating-point reg.
+ .macro vlxr regtype const
+ .irp regindex, 0, 14, 28, 31
+ vldr \regtype\regindex, \const
+ .endr
+ .endm
+
+ .macro vlxreq regtype const
+ .irp regindex, 0, 14, 28, 31
+ vldreq \regtype\regindex, \const
+ .endr
+ .endm
+
+ .macro vlxrmi regtype const
+ .irp regindex, 0, 14, 28, 31
+ vldrmi \regtype\regindex, \const
+ .endr
+ .endm
+
+ vlxr s "=0"
+ vlxr s "=0xff000000"
+ vlxr s "=-1"
+ vlxr s "=0x0fff0000"
+ .pool
+
+ vlxr s "=0"
+ vlxr s "=0x00ff0000"
+ vlxr s "=0xff00ffff"
+ vlxr s "=0x00fff000"
+ .pool
+
+ vlxreq s "=0"
+ vlxreq s "=0x0000ff00"
+ vlxreq s "=0xffff00ff"
+ vlxreq s "=0x000fff00"
+ .pool
+
+ vlxrmi s "=0"
+ vlxrmi s "=0x000000ff"
+ vlxrmi s "=0xffffff00"
+ vlxrmi s "=0x0000fff0"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0xca000000"
+ vlxr d "=-1"
+ vlxr d "=0x0fff0000"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0x00ff0000"
+ vlxr d "=0xff0000ff"
+ vlxr d "=0x00fff000"
+ .pool
+
+ vlxreq d "=0"
+ vlxreq d "=0x0000ff00"
+ vlxreq d "=0xffff00ff"
+ vlxreq d "=0x000fff00"
+ .pool
+
+ vlxrmi d "=0"
+ vlxrmi d "=0x000000ff"
+ vlxrmi d "=0xffffff00"
+ vlxrmi d "=0x0000ffff"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0xff00000000000000"
+ vlxr d "=-1"
+ vlxr d "=0x0fff000000000000"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0x00ff00000000000"
+ vlxr d "=0xff00ffff0000000"
+ vlxr d "=0x00fff0000000000"
+ .pool
+
+ vlxreq d "=0"
+ vlxreq d "=0x0000ff0000000000"
+ vlxreq d "=0xffff00ff00000000"
+ vlxreq d "=0x000fff0000000000"
+ .pool
+
+ vlxrmi d "=0"
+ vlxrmi d "=0x000000ff00000000"
+ vlxrmi d "=0xffffff0000000000"
+ vlxrmi d "=0x0000fff000000000"
+ .pool
+
+ # pool should be aligned to 8-byte.
+ .p2align 3
+ vldr d1, =0x0000fff000000000
+ .pool
+
+ # no error when code is align already.
+ .p2align 3
+ add r0, r1, #0
+ vldr d1, =0x0000fff000000000
+ .pool
+
+ .p2align 3
+ vldr d1, =0x0000fff000000000
+ vldr s2, =0xff000000
+ # padding A
+ vldr d3, =0x0000fff000000001
+ # reuse padding slot A
+ vldr s4, =0xff000001
+ # reuse d3
+ vldr d5, =0x0000fff000000001
+ # new 8-byte entry
+ vldr d6, =0x0000fff000000002
+ # new 8-byte entry
+ vldr d7, =0x0000fff000000003
+ # new 4-byte entry
+ vldr s8, =0xff000002
+ # padding B
+ vldr d9, =0x0000fff000000004
+ # reuse padding slot B
+ vldr s10, =0xff000003
+ # new 8-byte entry
+ vldr d11, =0x0000fff000000005
+ # new 4 entry
+ vldr s12, =0xff000004
+ # new 4 entry
+ vldr s13, =0xff000005
+ # reuse value of s4 in pool
+ vldr s14, =0xff000001
+ # reuse high part of d1 in pool
+ vldr s15, =0x0000fff0
+ # 8-byte entry reuse two 4-byte entries.
+ # this reuse should only happen for
+ # little-endian
+ # d16 reuse s12, s13
+ vldr d16, =0xff000005ff000004
+ # d17 should not reuse high part of d11 and s12.
+ # because the it's align 8-byte aligned.
+ vldr d17, =0xff0000040000fff0
+ .pool
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: ARM vldr with immediate constant (Big Endian)
+#as: -mcpu=arm7m -mbig-endian
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
+#source: vldconst.s
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+00000000 <foo> ed9f0a0e vldr s0, \[pc, #56\] ; 00000040 <foo\+0x40>
+00000004 <foo\+0x4> ed9f7a0d vldr s14, \[pc, #52\] ; 00000040 <foo\+0x40>
+00000008 <foo\+0x8> ed9fea0c vldr s28, \[pc, #48\] ; 00000040 <foo\+0x40>
+0000000c <foo\+0xc> eddffa0b vldr s31, \[pc, #44\] ; 00000040 <foo\+0x40>
+00000010 <foo\+0x10> ed9f0a0b vldr s0, \[pc, #44\] ; 00000044 <foo\+0x44>
+00000014 <foo\+0x14> ed9f7a0a vldr s14, \[pc, #40\] ; 00000044 <foo\+0x44>
+00000018 <foo\+0x18> ed9fea09 vldr s28, \[pc, #36\] ; 00000044 <foo\+0x44>
+0000001c <foo\+0x1c> eddffa08 vldr s31, \[pc, #32\] ; 00000044 <foo\+0x44>
+00000020 <foo\+0x20> ed9f0a08 vldr s0, \[pc, #32\] ; 00000048 <foo\+0x48>
+00000024 <foo\+0x24> ed9f7a07 vldr s14, \[pc, #28\] ; 00000048 <foo\+0x48>
+00000028 <foo\+0x28> ed9fea06 vldr s28, \[pc, #24\] ; 00000048 <foo\+0x48>
+0000002c <foo\+0x2c> eddffa05 vldr s31, \[pc, #20\] ; 00000048 <foo\+0x48>
+00000030 <foo\+0x30> ed9f0a05 vldr s0, \[pc, #20\] ; 0000004c <foo\+0x4c>
+00000034 <foo\+0x34> ed9f7a04 vldr s14, \[pc, #16\] ; 0000004c <foo\+0x4c>
+00000038 <foo\+0x38> ed9fea03 vldr s28, \[pc, #12\] ; 0000004c <foo\+0x4c>
+0000003c <foo\+0x3c> eddffa02 vldr s31, \[pc, #8\] ; 0000004c <foo\+0x4c>
+00000040 <foo\+0x40> 00000000 .word 0x00000000
+00000044 <foo\+0x44> ff000000 .word 0xff000000
+00000048 <foo\+0x48> ffffffff .word 0xffffffff
+0000004c <foo\+0x4c> 0fff0000 .word 0x0fff0000
+00000050 <foo\+0x50> ed9f0a0e vldr s0, \[pc, #56\] ; 00000090 <foo\+0x90>
+00000054 <foo\+0x54> ed9f7a0d vldr s14, \[pc, #52\] ; 00000090 <foo\+0x90>
+00000058 <foo\+0x58> ed9fea0c vldr s28, \[pc, #48\] ; 00000090 <foo\+0x90>
+0000005c <foo\+0x5c> eddffa0b vldr s31, \[pc, #44\] ; 00000090 <foo\+0x90>
+00000060 <foo\+0x60> ed9f0a0b vldr s0, \[pc, #44\] ; 00000094 <foo\+0x94>
+00000064 <foo\+0x64> ed9f7a0a vldr s14, \[pc, #40\] ; 00000094 <foo\+0x94>
+00000068 <foo\+0x68> ed9fea09 vldr s28, \[pc, #36\] ; 00000094 <foo\+0x94>
+0000006c <foo\+0x6c> eddffa08 vldr s31, \[pc, #32\] ; 00000094 <foo\+0x94>
+00000070 <foo\+0x70> ed9f0a08 vldr s0, \[pc, #32\] ; 00000098 <foo\+0x98>
+00000074 <foo\+0x74> ed9f7a07 vldr s14, \[pc, #28\] ; 00000098 <foo\+0x98>
+00000078 <foo\+0x78> ed9fea06 vldr s28, \[pc, #24\] ; 00000098 <foo\+0x98>
+0000007c <foo\+0x7c> eddffa05 vldr s31, \[pc, #20\] ; 00000098 <foo\+0x98>
+00000080 <foo\+0x80> ed9f0a05 vldr s0, \[pc, #20\] ; 0000009c <foo\+0x9c>
+00000084 <foo\+0x84> ed9f7a04 vldr s14, \[pc, #16\] ; 0000009c <foo\+0x9c>
+00000088 <foo\+0x88> ed9fea03 vldr s28, \[pc, #12\] ; 0000009c <foo\+0x9c>
+0000008c <foo\+0x8c> eddffa02 vldr s31, \[pc, #8\] ; 0000009c <foo\+0x9c>
+00000090 <foo\+0x90> 00000000 .word 0x00000000
+00000094 <foo\+0x94> 00ff0000 .word 0x00ff0000
+00000098 <foo\+0x98> ff00ffff .word 0xff00ffff
+0000009c <foo\+0x9c> 00fff000 .word 0x00fff000
+000000a0 <foo\+0xa0> 0d9f0a0e vldreq s0, \[pc, #56\] ; 000000e0 <foo\+0xe0>
+000000a4 <foo\+0xa4> 0d9f7a0d vldreq s14, \[pc, #52\] ; 000000e0 <foo\+0xe0>
+000000a8 <foo\+0xa8> 0d9fea0c vldreq s28, \[pc, #48\] ; 000000e0 <foo\+0xe0>
+000000ac <foo\+0xac> 0ddffa0b vldreq s31, \[pc, #44\] ; 000000e0 <foo\+0xe0>
+000000b0 <foo\+0xb0> 0d9f0a0b vldreq s0, \[pc, #44\] ; 000000e4 <foo\+0xe4>
+000000b4 <foo\+0xb4> 0d9f7a0a vldreq s14, \[pc, #40\] ; 000000e4 <foo\+0xe4>
+000000b8 <foo\+0xb8> 0d9fea09 vldreq s28, \[pc, #36\] ; 000000e4 <foo\+0xe4>
+000000bc <foo\+0xbc> 0ddffa08 vldreq s31, \[pc, #32\] ; 000000e4 <foo\+0xe4>
+000000c0 <foo\+0xc0> 0d9f0a08 vldreq s0, \[pc, #32\] ; 000000e8 <foo\+0xe8>
+000000c4 <foo\+0xc4> 0d9f7a07 vldreq s14, \[pc, #28\] ; 000000e8 <foo\+0xe8>
+000000c8 <foo\+0xc8> 0d9fea06 vldreq s28, \[pc, #24\] ; 000000e8 <foo\+0xe8>
+000000cc <foo\+0xcc> 0ddffa05 vldreq s31, \[pc, #20\] ; 000000e8 <foo\+0xe8>
+000000d0 <foo\+0xd0> 0d9f0a05 vldreq s0, \[pc, #20\] ; 000000ec <foo\+0xec>
+000000d4 <foo\+0xd4> 0d9f7a04 vldreq s14, \[pc, #16\] ; 000000ec <foo\+0xec>
+000000d8 <foo\+0xd8> 0d9fea03 vldreq s28, \[pc, #12\] ; 000000ec <foo\+0xec>
+000000dc <foo\+0xdc> 0ddffa02 vldreq s31, \[pc, #8\] ; 000000ec <foo\+0xec>
+000000e0 <foo\+0xe0> 00000000 .word 0x00000000
+000000e4 <foo\+0xe4> 0000ff00 .word 0x0000ff00
+000000e8 <foo\+0xe8> ffff00ff .word 0xffff00ff
+000000ec <foo\+0xec> 000fff00 .word 0x000fff00
+000000f0 <foo\+0xf0> 4d9f0a0e vldrmi s0, \[pc, #56\] ; 00000130 <foo\+0x130>
+000000f4 <foo\+0xf4> 4d9f7a0d vldrmi s14, \[pc, #52\] ; 00000130 <foo\+0x130>
+000000f8 <foo\+0xf8> 4d9fea0c vldrmi s28, \[pc, #48\] ; 00000130 <foo\+0x130>
+000000fc <foo\+0xfc> 4ddffa0b vldrmi s31, \[pc, #44\] ; 00000130 <foo\+0x130>
+00000100 <foo\+0x100> 4d9f0a0b vldrmi s0, \[pc, #44\] ; 00000134 <foo\+0x134>
+00000104 <foo\+0x104> 4d9f7a0a vldrmi s14, \[pc, #40\] ; 00000134 <foo\+0x134>
+00000108 <foo\+0x108> 4d9fea09 vldrmi s28, \[pc, #36\] ; 00000134 <foo\+0x134>
+0000010c <foo\+0x10c> 4ddffa08 vldrmi s31, \[pc, #32\] ; 00000134 <foo\+0x134>
+00000110 <foo\+0x110> 4d9f0a08 vldrmi s0, \[pc, #32\] ; 00000138 <foo\+0x138>
+00000114 <foo\+0x114> 4d9f7a07 vldrmi s14, \[pc, #28\] ; 00000138 <foo\+0x138>
+00000118 <foo\+0x118> 4d9fea06 vldrmi s28, \[pc, #24\] ; 00000138 <foo\+0x138>
+0000011c <foo\+0x11c> 4ddffa05 vldrmi s31, \[pc, #20\] ; 00000138 <foo\+0x138>
+00000120 <foo\+0x120> 4d9f0a05 vldrmi s0, \[pc, #20\] ; 0000013c <foo\+0x13c>
+00000124 <foo\+0x124> 4d9f7a04 vldrmi s14, \[pc, #16\] ; 0000013c <foo\+0x13c>
+00000128 <foo\+0x128> 4d9fea03 vldrmi s28, \[pc, #12\] ; 0000013c <foo\+0x13c>
+0000012c <foo\+0x12c> 4ddffa02 vldrmi s31, \[pc, #8\] ; 0000013c <foo\+0x13c>
+00000130 <foo\+0x130> 00000000 .word 0x00000000
+00000134 <foo\+0x134> 000000ff .word 0x000000ff
+00000138 <foo\+0x138> ffffff00 .word 0xffffff00
+0000013c <foo\+0x13c> 0000fff0 .word 0x0000fff0
+00000140 <foo\+0x140> f2800e30 vmov.i64 d0, #0x0000000000000000
+00000144 <foo\+0x144> f280ee30 vmov.i64 d14, #0x0000000000000000
+00000148 <foo\+0x148> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+0000014c <foo\+0x14c> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+00000150 <foo\+0x150> ed9f0b0a vldr d0, \[pc, #40\] ; 00000180 <foo\+0x180>
+00000154 <foo\+0x154> ed9feb09 vldr d14, \[pc, #36\] ; 00000180 <foo\+0x180>
+00000158 <foo\+0x158> eddfcb08 vldr d28, \[pc, #32\] ; 00000180 <foo\+0x180>
+0000015c <foo\+0x15c> eddffb07 vldr d31, \[pc, #28\] ; 00000180 <foo\+0x180>
+00000160 <foo\+0x160> f3870e3f vmov.i64 d0, #0xffffffffffffffff
+00000164 <foo\+0x164> f387ee3f vmov.i64 d14, #0xffffffffffffffff
+00000168 <foo\+0x168> f3c7ce3f vmov.i64 d28, #0xffffffffffffffff
+0000016c <foo\+0x16c> f3c7fe3f vmov.i64 d31, #0xffffffffffffffff
+00000170 <foo\+0x170> ed9f0b04 vldr d0, \[pc, #16\] ; 00000188 <foo\+0x188>
+00000174 <foo\+0x174> ed9feb03 vldr d14, \[pc, #12\] ; 00000188 <foo\+0x188>
+00000178 <foo\+0x178> eddfcb02 vldr d28, \[pc, #8\] ; 00000188 <foo\+0x188>
+0000017c <foo\+0x17c> eddffb01 vldr d31, \[pc, #4\] ; 00000188 <foo\+0x188>
+00000180 <foo\+0x180> 00000000 .word 0x00000000
+00000184 <foo\+0x184> ca000000 .word 0xca000000
+00000188 <foo\+0x188> 00000000 .word 0x00000000
+0000018c <foo\+0x18c> 0fff0000 .word 0x0fff0000
+00000190 <foo\+0x190> f2800e30 vmov.i64 d0, #0x0000000000000000
+00000194 <foo\+0x194> f280ee30 vmov.i64 d14, #0x0000000000000000
+00000198 <foo\+0x198> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+0000019c <foo\+0x19c> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+000001a0 <foo\+0x1a0> f2800e34 vmov.i64 d0, #0x0000000000ff0000
+000001a4 <foo\+0x1a4> f280ee34 vmov.i64 d14, #0x0000000000ff0000
+000001a8 <foo\+0x1a8> f2c0ce34 vmov.i64 d28, #0x0000000000ff0000
+000001ac <foo\+0x1ac> f2c0fe34 vmov.i64 d31, #0x0000000000ff0000
+000001b0 <foo\+0x1b0> f2800e39 vmov.i64 d0, #0x00000000ff0000ff
+000001b4 <foo\+0x1b4> f280ee39 vmov.i64 d14, #0x00000000ff0000ff
+000001b8 <foo\+0x1b8> f2c0ce39 vmov.i64 d28, #0x00000000ff0000ff
+000001bc <foo\+0x1bc> f2c0fe39 vmov.i64 d31, #0x00000000ff0000ff
+000001c0 <foo\+0x1c0> ed9f0b02 vldr d0, \[pc, #8\] ; 000001d0 <foo\+0x1d0>
+000001c4 <foo\+0x1c4> ed9feb01 vldr d14, \[pc, #4\] ; 000001d0 <foo\+0x1d0>
+000001c8 <foo\+0x1c8> eddfcb00 vldr d28, \[pc\] ; 000001d0 <foo\+0x1d0>
+000001cc <foo\+0x1cc> ed5ffb01 vldr d31, \[pc, #-4\] ; 000001d0 <foo\+0x1d0>
+000001d0 <foo\+0x1d0> 00000000 .word 0x00000000
+000001d4 <foo\+0x1d4> 00fff000 .word 0x00fff000
+000001d8 <foo\+0x1d8> f2800e30 vmov.i64 d0, #0x0000000000000000
+000001dc <foo\+0x1dc> f280ee30 vmov.i64 d14, #0x0000000000000000
+000001e0 <foo\+0x1e0> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+000001e4 <foo\+0x1e4> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+000001e8 <foo\+0x1e8> f2800e32 vmov.i64 d0, #0x000000000000ff00
+000001ec <foo\+0x1ec> f280ee32 vmov.i64 d14, #0x000000000000ff00
+000001f0 <foo\+0x1f0> f2c0ce32 vmov.i64 d28, #0x000000000000ff00
+000001f4 <foo\+0x1f4> f2c0fe32 vmov.i64 d31, #0x000000000000ff00
+000001f8 <foo\+0x1f8> f2800e3d vmov.i64 d0, #0x00000000ffff00ff
+000001fc <foo\+0x1fc> f280ee3d vmov.i64 d14, #0x00000000ffff00ff
+00000200 <foo\+0x200> f2c0ce3d vmov.i64 d28, #0x00000000ffff00ff
+00000204 <foo\+0x204> f2c0fe3d vmov.i64 d31, #0x00000000ffff00ff
+00000208 <foo\+0x208> 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000218 <foo\+0x218>
+0000020c <foo\+0x20c> 0d9feb01 vldreq d14, \[pc, #4\] ; 00000218 <foo\+0x218>
+00000210 <foo\+0x210> 0ddfcb00 vldreq d28, \[pc\] ; 00000218 <foo\+0x218>
+00000214 <foo\+0x214> 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000218 <foo\+0x218>
+00000218 <foo\+0x218> 00000000 .word 0x00000000
+0000021c <foo\+0x21c> 000fff00 .word 0x000fff00
+00000220 <foo\+0x220> f2800e30 vmov.i64 d0, #0x0000000000000000
+00000224 <foo\+0x224> f280ee30 vmov.i64 d14, #0x0000000000000000
+00000228 <foo\+0x228> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+0000022c <foo\+0x22c> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+00000230 <foo\+0x230> f2800e31 vmov.i64 d0, #0x00000000000000ff
+00000234 <foo\+0x234> f280ee31 vmov.i64 d14, #0x00000000000000ff
+00000238 <foo\+0x238> f2c0ce31 vmov.i64 d28, #0x00000000000000ff
+0000023c <foo\+0x23c> f2c0fe31 vmov.i64 d31, #0x00000000000000ff
+00000240 <foo\+0x240> f2800e3e vmov.i64 d0, #0x00000000ffffff00
+00000244 <foo\+0x244> f280ee3e vmov.i64 d14, #0x00000000ffffff00
+00000248 <foo\+0x248> f2c0ce3e vmov.i64 d28, #0x00000000ffffff00
+0000024c <foo\+0x24c> f2c0fe3e vmov.i64 d31, #0x00000000ffffff00
+00000250 <foo\+0x250> f2800e33 vmov.i64 d0, #0x000000000000ffff
+00000254 <foo\+0x254> f280ee33 vmov.i64 d14, #0x000000000000ffff
+00000258 <foo\+0x258> f2c0ce33 vmov.i64 d28, #0x000000000000ffff
+0000025c <foo\+0x25c> f2c0fe33 vmov.i64 d31, #0x000000000000ffff
+00000260 <foo\+0x260> f2800e30 vmov.i64 d0, #0x0000000000000000
+00000264 <foo\+0x264> f280ee30 vmov.i64 d14, #0x0000000000000000
+00000268 <foo\+0x268> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+0000026c <foo\+0x26c> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+00000270 <foo\+0x270> f3800e30 vmov.i64 d0, #0xff00000000000000
+00000274 <foo\+0x274> f380ee30 vmov.i64 d14, #0xff00000000000000
+00000278 <foo\+0x278> f3c0ce30 vmov.i64 d28, #0xff00000000000000
+0000027c <foo\+0x27c> f3c0fe30 vmov.i64 d31, #0xff00000000000000
+00000280 <foo\+0x280> f3870e3f vmov.i64 d0, #0xffffffffffffffff
+00000284 <foo\+0x284> f387ee3f vmov.i64 d14, #0xffffffffffffffff
+00000288 <foo\+0x288> f3c7ce3f vmov.i64 d28, #0xffffffffffffffff
+0000028c <foo\+0x28c> f3c7fe3f vmov.i64 d31, #0xffffffffffffffff
+00000290 <foo\+0x290> ed9f0b02 vldr d0, \[pc, #8\] ; 000002a0 <foo\+0x2a0>
+00000294 <foo\+0x294> ed9feb01 vldr d14, \[pc, #4\] ; 000002a0 <foo\+0x2a0>
+00000298 <foo\+0x298> eddfcb00 vldr d28, \[pc\] ; 000002a0 <foo\+0x2a0>
+0000029c <foo\+0x29c> ed5ffb01 vldr d31, \[pc, #-4\] ; 000002a0 <foo\+0x2a0>
+000002a0 <foo\+0x2a0> 0fff0000 .word 0x0fff0000
+000002a4 <foo\+0x2a4> 00000000 .word 0x00000000
+000002a8 <foo\+0x2a8> f2800e30 vmov.i64 d0, #0x0000000000000000
+000002ac <foo\+0x2ac> f280ee30 vmov.i64 d14, #0x0000000000000000
+000002b0 <foo\+0x2b0> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+000002b4 <foo\+0x2b4> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+000002b8 <foo\+0x2b8> ed9f0b0a vldr d0, \[pc, #40\] ; 000002e8 <foo\+0x2e8>
+000002bc <foo\+0x2bc> ed9feb09 vldr d14, \[pc, #36\] ; 000002e8 <foo\+0x2e8>
+000002c0 <foo\+0x2c0> eddfcb08 vldr d28, \[pc, #32\] ; 000002e8 <foo\+0x2e8>
+000002c4 <foo\+0x2c4> eddffb07 vldr d31, \[pc, #28\] ; 000002e8 <foo\+0x2e8>
+000002c8 <foo\+0x2c8> ed9f0b08 vldr d0, \[pc, #32\] ; 000002f0 <foo\+0x2f0>
+000002cc <foo\+0x2cc> ed9feb07 vldr d14, \[pc, #28\] ; 000002f0 <foo\+0x2f0>
+000002d0 <foo\+0x2d0> eddfcb06 vldr d28, \[pc, #24\] ; 000002f0 <foo\+0x2f0>
+000002d4 <foo\+0x2d4> eddffb05 vldr d31, \[pc, #20\] ; 000002f0 <foo\+0x2f0>
+000002d8 <foo\+0x2d8> ed9f0b06 vldr d0, \[pc, #24\] ; 000002f8 <foo\+0x2f8>
+000002dc <foo\+0x2dc> ed9feb05 vldr d14, \[pc, #20\] ; 000002f8 <foo\+0x2f8>
+000002e0 <foo\+0x2e0> eddfcb04 vldr d28, \[pc, #16\] ; 000002f8 <foo\+0x2f8>
+000002e4 <foo\+0x2e4> eddffb03 vldr d31, \[pc, #12\] ; 000002f8 <foo\+0x2f8>
+000002e8 <foo\+0x2e8> 000ff000 .word 0x000ff000
+000002ec <foo\+0x2ec> 00000000 .word 0x00000000
+000002f0 <foo\+0x2f0> 0ff00fff .word 0x0ff00fff
+000002f4 <foo\+0x2f4> f0000000 .word 0xf0000000
+000002f8 <foo\+0x2f8> 000fff00 .word 0x000fff00
+000002fc <foo\+0x2fc> 00000000 .word 0x00000000
+00000300 <foo\+0x300> f2800e30 vmov.i64 d0, #0x0000000000000000
+00000304 <foo\+0x304> f280ee30 vmov.i64 d14, #0x0000000000000000
+00000308 <foo\+0x308> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+0000030c <foo\+0x30c> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+00000310 <foo\+0x310> f2820e30 vmov.i64 d0, #0x0000ff0000000000
+00000314 <foo\+0x314> f282ee30 vmov.i64 d14, #0x0000ff0000000000
+00000318 <foo\+0x318> f2c2ce30 vmov.i64 d28, #0x0000ff0000000000
+0000031c <foo\+0x31c> f2c2fe30 vmov.i64 d31, #0x0000ff0000000000
+00000320 <foo\+0x320> f3850e30 vmov.i64 d0, #0xffff00ff00000000
+00000324 <foo\+0x324> f385ee30 vmov.i64 d14, #0xffff00ff00000000
+00000328 <foo\+0x328> f3c5ce30 vmov.i64 d28, #0xffff00ff00000000
+0000032c <foo\+0x32c> f3c5fe30 vmov.i64 d31, #0xffff00ff00000000
+00000330 <foo\+0x330> 0d9f0b02 vldreq d0, \[pc, #8\] ; 00000340 <foo\+0x340>
+00000334 <foo\+0x334> 0d9feb01 vldreq d14, \[pc, #4\] ; 00000340 <foo\+0x340>
+00000338 <foo\+0x338> 0ddfcb00 vldreq d28, \[pc\] ; 00000340 <foo\+0x340>
+0000033c <foo\+0x33c> 0d5ffb01 vldreq d31, \[pc, #-4\] ; 00000340 <foo\+0x340>
+00000340 <foo\+0x340> 000fff00 .word 0x000fff00
+00000344 <foo\+0x344> 00000000 .word 0x00000000
+00000348 <foo\+0x348> f2800e30 vmov.i64 d0, #0x0000000000000000
+0000034c <foo\+0x34c> f280ee30 vmov.i64 d14, #0x0000000000000000
+00000350 <foo\+0x350> f2c0ce30 vmov.i64 d28, #0x0000000000000000
+00000354 <foo\+0x354> f2c0fe30 vmov.i64 d31, #0x0000000000000000
+00000358 <foo\+0x358> f2810e30 vmov.i64 d0, #0x000000ff00000000
+0000035c <foo\+0x35c> f281ee30 vmov.i64 d14, #0x000000ff00000000
+00000360 <foo\+0x360> f2c1ce30 vmov.i64 d28, #0x000000ff00000000
+00000364 <foo\+0x364> f2c1fe30 vmov.i64 d31, #0x000000ff00000000
+00000368 <foo\+0x368> f3860e30 vmov.i64 d0, #0xffffff0000000000
+0000036c <foo\+0x36c> f386ee30 vmov.i64 d14, #0xffffff0000000000
+00000370 <foo\+0x370> f3c6ce30 vmov.i64 d28, #0xffffff0000000000
+00000374 <foo\+0x374> f3c6fe30 vmov.i64 d31, #0xffffff0000000000
+00000378 <foo\+0x378> 4d9f0b02 vldrmi d0, \[pc, #8\] ; 00000388 <foo\+0x388>
+0000037c <foo\+0x37c> 4d9feb01 vldrmi d14, \[pc, #4\] ; 00000388 <foo\+0x388>
+00000380 <foo\+0x380> 4ddfcb00 vldrmi d28, \[pc\] ; 00000388 <foo\+0x388>
+00000384 <foo\+0x384> 4d5ffb01 vldrmi d31, \[pc, #-4\] ; 00000388 <foo\+0x388>
+00000388 <foo\+0x388> 0000fff0 .word 0x0000fff0
+0000038c <foo\+0x38c> 00000000 .word 0x00000000
+00000390 <foo\+0x390> ed9f1b00 vldr d1, \[pc\] ; 00000398 <foo\+0x398>
+00000394 <foo\+0x394> 00000000 andeq r0, r0, r0
+00000398 <foo\+0x398> 0000fff0 .word 0x0000fff0
+0000039c <foo\+0x39c> 00000000 .word 0x00000000
+000003a0 <foo\+0x3a0> e2810000 add r0, r1, #0
+000003a4 <foo\+0x3a4> ed1f1b01 vldr d1, \[pc, #-4\] ; 000003a8 <foo\+0x3a8>
+000003a8 <foo\+0x3a8> 0000fff0 .word 0x0000fff0
+000003ac <foo\+0x3ac> 00000000 .word 0x00000000
+000003b0 <foo\+0x3b0> ed9f1b10 vldr d1, \[pc, #64\] ; 000003f8 <foo\+0x3f8>
+000003b4 <foo\+0x3b4> ed9f1a11 vldr s2, \[pc, #68\] ; 00000400 <foo\+0x400>
+000003b8 <foo\+0x3b8> ed9f3b12 vldr d3, \[pc, #72\] ; 00000408 <foo\+0x408>
+000003bc <foo\+0x3bc> ed9f2a10 vldr s4, \[pc, #64\] ; 00000404 <foo\+0x404>
+000003c0 <foo\+0x3c0> ed9f5b10 vldr d5, \[pc, #64\] ; 00000408 <foo\+0x408>
+000003c4 <foo\+0x3c4> ed9f6b11 vldr d6, \[pc, #68\] ; 00000410 <foo\+0x410>
+000003c8 <foo\+0x3c8> ed9f7b12 vldr d7, \[pc, #72\] ; 00000418 <foo\+0x418>
+000003cc <foo\+0x3cc> ed9f4a13 vldr s8, \[pc, #76\] ; 00000420 <foo\+0x420>
+000003d0 <foo\+0x3d0> ed9f9b14 vldr d9, \[pc, #80\] ; 00000428 <foo\+0x428>
+000003d4 <foo\+0x3d4> ed9f5a12 vldr s10, \[pc, #72\] ; 00000424 <foo\+0x424>
+000003d8 <foo\+0x3d8> ed9fbb14 vldr d11, \[pc, #80\] ; 00000430 <foo\+0x430>
+000003dc <foo\+0x3dc> ed9f6a15 vldr s12, \[pc, #84\] ; 00000438 <foo\+0x438>
+000003e0 <foo\+0x3e0> eddf6a15 vldr s13, \[pc, #84\] ; 0000043c <foo\+0x43c>
+000003e4 <foo\+0x3e4> ed9f7a06 vldr s14, \[pc, #24\] ; 00000404 <foo\+0x404>
+000003e8 <foo\+0x3e8> eddf7a02 vldr s15, \[pc, #8\] ; 000003f8 <foo\+0x3f8>
+000003ec <foo\+0x3ec> eddf0b13 vldr d16, \[pc, #76\] ; 00000440 <foo\+0x440>
+000003f0 <foo\+0x3f0> eddf1b14 vldr d17, \[pc, #80\] ; 00000448 <foo\+0x448>
+000003f4 <foo\+0x3f4> 00000000 andeq r0, r0, r0
+000003f8 <foo\+0x3f8> 0000fff0 .word 0x0000fff0
+000003fc <foo\+0x3fc> 00000000 .word 0x00000000
+00000400 <foo\+0x400> ff000000 .word 0xff000000
+00000404 <foo\+0x404> ff000001 .word 0xff000001
+00000408 <foo\+0x408> 0000fff0 .word 0x0000fff0
+0000040c <foo\+0x40c> 00000001 .word 0x00000001
+00000410 <foo\+0x410> 0000fff0 .word 0x0000fff0
+00000414 <foo\+0x414> 00000002 .word 0x00000002
+00000418 <foo\+0x418> 0000fff0 .word 0x0000fff0
+0000041c <foo\+0x41c> 00000003 .word 0x00000003
+00000420 <foo\+0x420> ff000002 .word 0xff000002
+00000424 <foo\+0x424> ff000003 .word 0xff000003
+00000428 <foo\+0x428> 0000fff0 .word 0x0000fff0
+0000042c <foo\+0x42c> 00000004 .word 0x00000004
+00000430 <foo\+0x430> 0000fff0 .word 0x0000fff0
+00000434 <foo\+0x434> 00000005 .word 0x00000005
+00000438 <foo\+0x438> ff000004 .word 0xff000004
+0000043c <foo\+0x43c> ff000005 .word 0xff000005
+00000440 <foo\+0x440> ff000005 .word 0xff000005
+00000444 <foo\+0x444> ff000004 .word 0xff000004
+00000448 <foo\+0x448> ff000004 .word 0xff000004
+0000044c <foo\+0x44c> 0000fff0 .word 0x0000fff0
projects / platform / upstream / binutils.git / commitdiff