Add x86-64-opcode (checks valid opcodes) and x86-64-inval (checks invalid opcodes...

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index e067808bf9d1384b194f809bde38eb39677e1f77..a6fcc0c34c9828911c49e61bcd5511f03c1547f0 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2002-02-22  Bo Thorsen  <bo@suse.de>
+
+       * i386.exp: Add x86-64-opcode (checks valid opcodes) and x86-64-inval
+       (checks invalid opcodes) checks
+       * x86-64-inval.l: New file.
+       * x86-64-inval.s: New file.
+       * x86-64-opcode.d: New file.
+       * x86-64-opcode.s: New file.
+
 2002-02-26  Chris Demetriou  <cgd@broadcom.com>
 
        * gas/mips/empic2.d: Adjust for the fact that relocations on

diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index e5ba382a5b8fd0cb8d7e9871d079981232d9c7fa..e66468090ff357db14e329b66f1305ccfc8b3b73 100644 (file)
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -87,6 +87,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     set ASFLAGS "$ASFLAGS --64"
 
     run_dump_test "x86_64"
+    run_dump_test "x86-64-opcode"
+    run_list_test "x86-64-inval" "-al"
 
     set ASFLAGS "$old_ASFLAGS"
 }

diff --git a/gas/testsuite/gas/i386/x86-64-inval.l b/gas/testsuite/gas/i386/x86-64-inval.l
new file mode 100644 (file)
index 0000000..05416d7
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-inval.l
@@ -0,0 +1,30 @@
+.*: Assembler messages:
+.*:3: Error: .*
+.*:4: Error: .*
+.*:5: Error: .*
+.*:6: Error: .*
+.*:7: Error: .*
+.*:8: Error: .*
+.*:9: Error: .*
+.*:10: Error: .*
+.*:11: Error: .*
+.*:12: Error: .*
+.*:13: Error: .*
+.*:14: Error: .*
+GAS LISTING .*
+
+
+   1 [         ]*      .text
+   2 [         ]*# All the following should be illegal for x86-64
+   3 [         ]*calll \*%eax  # 32-bit data size not allowed
+   4 [         ]*calll \*\(%ax\)       # 32-bit data size not allowed
+   5 [         ]*calll \*\(%eax\)      # 32-bit data size not allowed
+   6 [         ]*calll \*\(%r8\)       # 32-bit data size not allowed
+   7 [         ]*calll \*\(%rax\)      # 32-bit data size not allowed
+   8 [         ]*callq \*\(%ax\)       # 32-bit data size not allowed
+   9 [         ]*callw \*\(%ax\)       # no 16-bit addressing
+  10 [         ]*foo:[         ]*jcxz foo      # No prefix exists to select CX as a counter
+  11 [         ]*popl %eax     # can\'t have 32-bit stack operands
+  12 [         ]*pushl %eax    # can\'t have 32-bit stack operands
+  13 [         ]*pushfl                # can\'t have 32-bit stack operands
+  14 [         ]*popfl         # can\'t have 32-bit stack operands

diff --git a/gas/testsuite/gas/i386/x86-64-inval.s b/gas/testsuite/gas/i386/x86-64-inval.s
new file mode 100644 (file)
index 0000000..be532d5
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-inval.s
@@ -0,0 +1,14 @@
+       .text
+# All the following should be illegal for x86-64
+       calll *%eax     # 32-bit data size not allowed
+        calll *(%ax)   # 32-bit data size not allowed
+        calll *(%eax)  # 32-bit data size not allowed
+        calll *(%r8)   # 32-bit data size not allowed
+        calll *(%rax)  # 32-bit data size not allowed
+        callq *(%ax)   # 32-bit data size not allowed
+        callw *(%ax)   # no 16-bit addressing
+foo:   jcxz foo        # No prefix exists to select CX as a counter
+        popl %eax      # can't have 32-bit stack operands
+        pushl %eax     # can't have 32-bit stack operands
+        pushfl         # can't have 32-bit stack operands
+       popfl           # can't have 32-bit stack operands

diff --git a/gas/testsuite/gas/i386/x86-64-opcode.d b/gas/testsuite/gas/i386/x86-64-opcode.d
new file mode 100644 (file)
index 0000000..e50a15f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-opcode.d
@@ -0,0 +1,260 @@
+#as: -J
+#objdump: -drw
+#name: x86-64 opcode
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[       ]*0:[   ]+41 ff 10[     ]+callq[        ]+\*\(%r8\)[    ]*(#.*)*
+[       ]*3:[   ]+ff 10[        ]+callq[        ]+\*\(%rax\)[   ]*(#.*)*
+[       ]*5:[   ]+41 ff 10[     ]+callq[        ]+\*\(%r8\)[    ]*(#.*)*
+[       ]*8:[   ]+ff 10[        ]+callq[        ]+\*\(%rax\)[   ]*(#.*)*
+[       ]*a:[   ]+cb[   ]+lret[         ]*(#.*)*
+[       ]*b:[   ]+c3[   ]+retq[         ]*(#.*)*
+[       ]*c:[   ]+cf[   ]+iret[         ]*(#.*)*
+[       ]*d:[   ]+66 cf[        ]+iretw[        ]*(#.*)*
+[       ]*f:[   ]+48 cf[        ]+iretq[        ]*(#.*)*
+[       ]*11:[  ]+66 41 8c 08[  ]+movw[         ]+%cs,\(%r8\)[  ]*(#.*)*
+[       ]*15:[  ]+66 8c 08[     ]+movw[         ]+%cs,\(%rax\)[         ]*(#.*)*
+[       ]*18:[  ]+66 41 8c 10[  ]+movw[         ]+%ss,\(%r8\)[  ]*(#.*)*
+[       ]*1c:[  ]+66 8c 10[     ]+movw[         ]+%ss,\(%rax\)[         ]*(#.*)*
+[       ]*1f:[  ]+66 41 8c 20[  ]+movw[         ]+%fs,\(%r8\)[  ]*(#.*)*
+[       ]*23:[  ]+66 8c 20[     ]+movw[         ]+%fs,\(%rax\)[         ]*(#.*)*
+[       ]*26:[  ]+41 8c 08[     ]+movl[         ]+%cs,\(%r8\)[  ]*(#.*)*
+[       ]*29:[  ]+8c 08[        ]+movl[         ]+%cs,\(%rax\)[         ]*(#.*)*
+[       ]*2b:[  ]+41 8c 10[     ]+movl[         ]+%ss,\(%r8\)[  ]*(#.*)*
+[       ]*2e:[  ]+8c 10[        ]+movl[         ]+%ss,\(%rax\)[         ]*(#.*)*
+[       ]*30:[  ]+41 8c 20[     ]+movl[         ]+%fs,\(%r8\)[  ]*(#.*)*
+[       ]*33:[  ]+8c 20[        ]+movl[         ]+%fs,\(%rax\)[         ]*(#.*)*
+[       ]*35:[  ]+41 8e 10[     ]+movl[         ]+\(%r8\),%ss[  ]*(#.*)*
+[       ]*38:[  ]+8e 10[        ]+movl[         ]+\(%rax\),%ss[         ]*(#.*)*
+[       ]*3a:[  ]+41 8e 20[     ]+movl[         ]+\(%r8\),%fs[  ]*(#.*)*
+[       ]*3d:[  ]+8e 20[        ]+movl[         ]+\(%rax\),%fs[         ]*(#.*)*
+[       ]*3f:[  ]+41 c6 00 00[  ]+movb[         ]+\$0[x0]*,\(%r8\)[     ]*(#.*)*
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+[       ]*51:[  ]+c7 00 00 00 00 70[    ]+movl[         ]+\$0x70000000,\(%rax\)[        ]*(#.*)*
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+[       ]*209:[         ]+f3 44 0f 2a f8[       ]+cvtsi2ss[     ]+%eax,%xmm15[  ]*(#.*)*
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+[       ]*239:[         ]+f3 0f 2a 38[  ]+cvtsi2ss[     ]+\(%rax\),%xmm7[       ]*(#.*)*
+[       ]*23d:[         ]+f2 41 0f 2a 00[       ]+cvtsi2sd[     ]+\(%r8\),%xmm0[        ]*(#.*)*
+[       ]*242:[         ]+f2 0f 2a 00[  ]+cvtsi2sd[     ]+\(%rax\),%xmm0[       ]*(#.*)*
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+[       ]*25f:[         ]+f2 0f 2a 38[  ]+cvtsi2sd[     ]+\(%rax\),%xmm7[       ]*(#.*)*
+[       ]*263:[         ]+f2 0f 2a c0[  ]+cvtsi2sd[     ]+%eax,%xmm0[   ]*(#.*)*
+[       ]*267:[         ]+f2 44 0f 2a f8[       ]+cvtsi2sd[     ]+%eax,%xmm15[  ]*(#.*)*
+[       ]*26c:[         ]+f2 44 0f 2a c0[       ]+cvtsi2sd[     ]+%eax,%xmm8[   ]*(#.*)*
+[       ]*271:[         ]+f2 0f 2a f8[  ]+cvtsi2sd[     ]+%eax,%xmm7[   ]*(#.*)*
+[       ]*275:[         ]+f2 41 0f 2a 00[       ]+cvtsi2sd[     ]+\(%r8\),%xmm0[        ]*(#.*)*
+[       ]*27a:[         ]+f2 0f 2a 00[  ]+cvtsi2sd[     ]+\(%rax\),%xmm0[       ]*(#.*)*
+[       ]*27e:[         ]+f2 45 0f 2a 38[       ]+cvtsi2sd[     ]+\(%r8\),%xmm15[       ]*(#.*)*
+[       ]*283:[         ]+f2 44 0f 2a 38[       ]+cvtsi2sd[     ]+\(%rax\),%xmm15[      ]*(#.*)*
+[       ]*288:[         ]+f2 45 0f 2a 00[       ]+cvtsi2sd[     ]+\(%r8\),%xmm8[        ]*(#.*)*
+[       ]*28d:[         ]+f2 44 0f 2a 00[       ]+cvtsi2sd[     ]+\(%rax\),%xmm8[       ]*(#.*)*
+[       ]*292:[         ]+f2 41 0f 2a 38[       ]+cvtsi2sd[     ]+\(%r8\),%xmm7[        ]*(#.*)*
+[       ]*297:[         ]+f2 0f 2a 38[  ]+cvtsi2sd[     ]+\(%rax\),%xmm7[       ]*(#.*)*
+[       ]*29b:[         ]+66 41 0f 6e 00[       ]+movd[         ]+\(%r8\),%xmm0[        ]*(#.*)*
+[       ]*2a0:[         ]+66 0f 6e 00[  ]+movd[         ]+\(%rax\),%xmm0[       ]*(#.*)*
+[       ]*2a4:[         ]+66 45 0f 6e 38[       ]+movd[         ]+\(%r8\),%xmm15[       ]*(#.*)*
+[       ]*2a9:[         ]+66 44 0f 6e 38[       ]+movd[         ]+\(%rax\),%xmm15[      ]*(#.*)*
+[       ]*2ae:[         ]+66 45 0f 6e 00[       ]+movd[         ]+\(%r8\),%xmm8[        ]*(#.*)*
+[       ]*2b3:[         ]+66 44 0f 6e 00[       ]+movd[         ]+\(%rax\),%xmm8[       ]*(#.*)*
+[       ]*2b8:[         ]+66 41 0f 6e 38[       ]+movd[         ]+\(%r8\),%xmm7[        ]*(#.*)*
+[       ]*2bd:[         ]+66 0f 6e 38[  ]+movd[         ]+\(%rax\),%xmm7[       ]*(#.*)*
+[       ]*2c1:[         ]+66 0f 6e c0[  ]+movd[         ]+%eax,%xmm0[   ]*(#.*)*
+[       ]*2c5:[         ]+66 44 0f 6e f8[       ]+movd[         ]+%eax,%xmm15[  ]*(#.*)*
+[       ]*2ca:[         ]+66 44 0f 6e c0[       ]+movd[         ]+%eax,%xmm8[   ]*(#.*)*
+[       ]*2cf:[         ]+66 0f 6e f8[  ]+movd[         ]+%eax,%xmm7[   ]*(#.*)*
+[       ]*2d3:[         ]+66 41 0f 7e 00[       ]+movd[         ]+%xmm0,\(%r8\)[        ]*(#.*)*
+[       ]*2d8:[         ]+66 0f 7e 00[  ]+movd[         ]+%xmm0,\(%rax\)[       ]*(#.*)*
+[       ]*2dc:[         ]+66 45 0f 7e 38[       ]+movd[         ]+%xmm15,\(%r8\)[       ]*(#.*)*
+[       ]*2e1:[         ]+66 44 0f 7e 38[       ]+movd[         ]+%xmm15,\(%rax\)[      ]*(#.*)*
+[       ]*2e6:[         ]+66 45 0f 7e 00[       ]+movd[         ]+%xmm8,\(%r8\)[        ]*(#.*)*
+[       ]*2eb:[         ]+66 44 0f 7e 00[       ]+movd[         ]+%xmm8,\(%rax\)[       ]*(#.*)*
+[       ]*2f0:[         ]+66 41 0f 7e 38[       ]+movd[         ]+%xmm7,\(%r8\)[        ]*(#.*)*
+[       ]*2f5:[         ]+66 0f 7e 38[  ]+movd[         ]+%xmm7,\(%rax\)[       ]*(#.*)*
+[       ]*2f9:[         ]+66 0f 7e c0[  ]+movd[         ]+%xmm0,%eax[   ]*(#.*)*
+[       ]*2fd:[         ]+66 44 0f 7e f8[       ]+movd[         ]+%xmm15,%eax[  ]*(#.*)*
+[       ]*302:[         ]+66 44 0f 7e c0[       ]+movd[         ]+%xmm8,%eax[   ]*(#.*)*
+[       ]*307:[         ]+66 0f 7e f8[  ]+movd[         ]+%xmm7,%eax[   ]*(#.*)*
+[       ]*30b:[         ]+f3 41 0f 7e 00[       ]+movq[         ]+\(%r8\),%xmm0[        ]*(#.*)*
+[       ]*310:[         ]+f3 0f 7e 00[  ]+movq[         ]+\(%rax\),%xmm0[       ]*(#.*)*
+[       ]*314:[         ]+f3 45 0f 7e 38[       ]+movq[         ]+\(%r8\),%xmm15[       ]*(#.*)*
+[       ]*319:[         ]+f3 44 0f 7e 38[       ]+movq[         ]+\(%rax\),%xmm15[      ]*(#.*)*
+[       ]*31e:[         ]+f3 45 0f 7e 00[       ]+movq[         ]+\(%r8\),%xmm8[        ]*(#.*)*
+[       ]*323:[         ]+f3 44 0f 7e 00[       ]+movq[         ]+\(%rax\),%xmm8[       ]*(#.*)*
+[       ]*328:[         ]+f3 41 0f 7e 38[       ]+movq[         ]+\(%r8\),%xmm7[        ]*(#.*)*
+[       ]*32d:[         ]+f3 0f 7e 38[  ]+movq[         ]+\(%rax\),%xmm7[       ]*(#.*)*
+[       ]*331:[         ]+f3 0f 7e c0[  ]+movq[         ]+%xmm0,%xmm0[  ]*(#.*)*
+[       ]*335:[         ]+f3 45 0f 7e ff[       ]+movq[         ]+%xmm15,%xmm15[        ]*(#.*)*
+[       ]*33a:[         ]+f3 45 0f 7e c7[       ]+movq[         ]+%xmm15,%xmm8[         ]*(#.*)*
+[       ]*33f:[         ]+f3 41 0f 7e ff[       ]+movq[         ]+%xmm15,%xmm7[         ]*(#.*)*
+[       ]*344:[         ]+f3 41 0f 7e c7[       ]+movq[         ]+%xmm15,%xmm0[         ]*(#.*)*
+[       ]*349:[         ]+f3 45 0f 7e f8[       ]+movq[         ]+%xmm8,%xmm15[         ]*(#.*)*
+[       ]*34e:[         ]+f3 45 0f 7e c0[       ]+movq[         ]+%xmm8,%xmm8[  ]*(#.*)*
+[       ]*353:[         ]+f3 41 0f 7e f8[       ]+movq[         ]+%xmm8,%xmm7[  ]*(#.*)*
+[       ]*358:[         ]+f3 41 0f 7e c0[       ]+movq[         ]+%xmm8,%xmm0[  ]*(#.*)*
+[       ]*35d:[         ]+f3 44 0f 7e ff[       ]+movq[         ]+%xmm7,%xmm15[         ]*(#.*)*
+[       ]*362:[         ]+f3 44 0f 7e c7[       ]+movq[         ]+%xmm7,%xmm8[  ]*(#.*)*
+[       ]*367:[         ]+f3 0f 7e ff[  ]+movq[         ]+%xmm7,%xmm7[  ]*(#.*)*
+[       ]*36b:[         ]+f3 0f 7e c7[  ]+movq[         ]+%xmm7,%xmm0[  ]*(#.*)*
+[       ]*36f:[         ]+f3 44 0f 7e f8[       ]+movq[         ]+%xmm0,%xmm15[         ]*(#.*)*
+[       ]*374:[         ]+f3 44 0f 7e c0[       ]+movq[         ]+%xmm0,%xmm8[  ]*(#.*)*
+[       ]*379:[         ]+f3 0f 7e f8[  ]+movq[         ]+%xmm0,%xmm7[  ]*(#.*)*
+[       ]*37d:[         ]+66 41 0f d6 00[       ]+movq[         ]+%xmm0,\(%r8\)[        ]*(#.*)*
+[       ]*382:[         ]+66 0f d6 00[  ]+movq[         ]+%xmm0,\(%rax\)[       ]*(#.*)*
+[       ]*386:[         ]+66 45 0f d6 38[       ]+movq[         ]+%xmm15,\(%r8\)[       ]*(#.*)*
+[       ]*38b:[         ]+66 44 0f d6 38[       ]+movq[         ]+%xmm15,\(%rax\)[      ]*(#.*)*
+[       ]*390:[         ]+66 45 0f d6 00[       ]+movq[         ]+%xmm8,\(%r8\)[        ]*(#.*)*
+[       ]*395:[         ]+66 44 0f d6 00[       ]+movq[         ]+%xmm8,\(%rax\)[       ]*(#.*)*
+[       ]*39a:[         ]+66 41 0f d6 38[       ]+movq[         ]+%xmm7,\(%r8\)[        ]*(#.*)*
+[       ]*39f:[         ]+41 0f 6e 00[  ]+movd[         ]+\(%r8\),%mm0[         ]*(#.*)*
+[       ]*3a3:[         ]+0f 6e 00[     ]+movd[         ]+\(%rax\),%mm0[        ]*(#.*)*
+[       ]*3a6:[         ]+41 0f 6e 38[  ]+movd[         ]+\(%r8\),%mm7[         ]*(#.*)*
+[       ]*3aa:[         ]+0f 6e 38[     ]+movd[         ]+\(%rax\),%mm7[        ]*(#.*)*
+[       ]*3ad:[         ]+0f 6e c0[     ]+movd[         ]+%eax,%mm0[    ]*(#.*)*
+[       ]*3b0:[         ]+0f 6e f8[     ]+movd[         ]+%eax,%mm7[    ]*(#.*)*
+[       ]*3b3:[         ]+41 0f 7e 00[  ]+movd[         ]+%mm0,\(%r8\)[         ]*(#.*)*
+[       ]*3b7:[         ]+0f 7e 00[     ]+movd[         ]+%mm0,\(%rax\)[        ]*(#.*)*
+[       ]*3ba:[         ]+41 0f 7e 38[  ]+movd[         ]+%mm7,\(%r8\)[         ]*(#.*)*
+[       ]*3be:[         ]+0f 7e 38[     ]+movd[         ]+%mm7,\(%rax\)[        ]*(#.*)*
+[       ]*3c1:[         ]+0f 7e c0[     ]+movd[         ]+%mm0,%eax[    ]*(#.*)*
+[       ]*3c4:[         ]+0f 7e f8[     ]+movd[         ]+%mm7,%eax[    ]*(#.*)*
+[       ]*3c7:[         ]+41 0f 6f 00[  ]+movq[         ]+\(%r8\),%mm0[         ]*(#.*)*
+[       ]*3cb:[         ]+0f 6f 00[     ]+movq[         ]+\(%rax\),%mm0[        ]*(#.*)*
+[       ]*3ce:[         ]+41 0f 6f 38[  ]+movq[         ]+\(%r8\),%mm7[         ]*(#.*)*
+[       ]*3d2:[         ]+0f 6f 38[     ]+movq[         ]+\(%rax\),%mm7[        ]*(#.*)*
+[       ]*3d5:[         ]+41 0f 7f 00[  ]+movq[         ]+%mm0,\(%r8\)[         ]*(#.*)*
+[       ]*3d9:[         ]+0f 7f 00[     ]+movq[         ]+%mm0,\(%rax\)[        ]*(#.*)*
+[       ]*3dc:[         ]+41 0f 7f 38[  ]+movq[         ]+%mm7,\(%r8\)[         ]*(#.*)*
+[       ]*3e0:[         ]+0f 7f 38[     ]+movq[         ]+%mm7,\(%rax\)[        ]*(#.*)*
+[       ]*3e3:[         ]+41 8f 00[     ]+popq[         ]+\(%r8\)[      ]*(#.*)*
+[       ]*3e6:[         ]+8f 00[        ]+popq[         ]+\(%rax\)[     ]*(#.*)*
+[       ]*3e8:[         ]+9d[   ]+popfq[        ]*(#.*)*
+[       ]*3e9:[         ]+41 ff 30[     ]+pushq[        ]+\(%r8\)[      ]*(#.*)*
+[       ]*3ec:[         ]+ff 30[        ]+pushq[        ]+\(%rax\)[     ]*(#.*)*
+[       ]*3ee:[         ]+9c[   ]+pushfq[       ]*(#.*)*
+[       ]*3ef:[         ]+0f 77[        ]+emms[         ]*(#.*)*
+[       ]*3f1:[         ]+0f 0e[        ]+femms[        ]*(#.*)*
+[       ]*3f3:[         ]+0f 08[        ]+invd[         ]*(#.*)*
+[       ]*3f5:[         ]+41 0f 01 38[  ]+invlpg[       ]+\(%r8\)[      ]*(#.*)*
+[       ]*3f9:[         ]+0f 01 38[     ]+invlpg[       ]+\(%rax\)[     ]*(#.*)*
+[       ]*3fc:[         ]+41 0f 01 38[  ]+invlpg[       ]+\(%r8\)[      ]*(#.*)*
+[       ]*400:[         ]+0f 01 38[     ]+invlpg[       ]+\(%rax\)[     ]*(#.*)*
+[       ]*403:[         ]+41 0f 01 38[  ]+invlpg[       ]+\(%r8\)[      ]*(#.*)*
+[       ]*407:[         ]+0f 01 38[     ]+invlpg[       ]+\(%rax\)[     ]*(#.*)*
+[       ]*40a:[         ]+0f 00 c0[     ]+sldt[         ]+%eax[         ]*(#.*)*
+[       ]*40d:[         ]+e6 00[        ]+out[  ]+%al,\$0[x0]*[         ]*(#.*)*
+[       ]*40f:[         ]+66 e7 00[     ]+out[  ]+%ax,\$0[x0]*[         ]*(#.*)*
+[       ]*412:[         ]+e7 00[        ]+out[  ]+%eax,\$0[x0]*[        ]*(#.*)*

diff --git a/gas/testsuite/gas/i386/x86-64-opcode.s b/gas/testsuite/gas/i386/x86-64-opcode.s
new file mode 100644 (file)
index 0000000..b7a42e0
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-opcode.s
@@ -0,0 +1,380 @@
+.text
+       #                                 Prefixes
+       #                               O16 A32 OV REX  OPCODE                           ; NOTES
+
+       # CALL
+       CALLq *(%r8)                  # --  --  -- 41   FF 10                            ; REX to access upper reg.
+       CALLq *(%rax)                 # --  --  -- --   FF 10
+       CALLq *(%r8)                  # --  --  -- 41   FF 10                            ; REX to access upper reg.
+       CALLq *(%rax)                 # --  --  -- --   FF 10
+                                       
+       # RET                           
+       lret                          # --  --  -- --   CB
+       retq                          # --  --  -- --   C3
+                                       
+       # IRET                          
+       IRET                          # --  --  -- --   CF                               ; 32-bit operand size
+       IRETW                         # 66  --  -- --   CF                               ; O16 for 16-bit operand size
+       IRETQ                         # --  --  -- 48   CF                               ; REX for 64-bit operand size
+                                       
+       # CMP                           
+                                       
+       # MOV                           
+       MOVw %cs,(%r8)                # 66  --  -- 41   8C 08                            ; REX to access upper reg. O16 for 16-bit operand size
+       MOVw %cs,(%rax)               # 66  --  -- --   8C 08                            ; O16 for 16-bit operand size
+       MOVw %ss,(%r8)                # 66  --  -- 41   8C 10                            ; REX to access upper reg. O16 for 16-bit operand size
+       MOVw %ss,(%rax)               # 66  --  -- --   8C 10                            ; O16 for 16-bit operand size
+       MOVw %fs,(%r8)                # 66  --  -- 41   8C 20                            ; REX to access upper reg. O16 for 16-bit operand size
+       MOVw %fs,(%rax)               # 66  --  -- --   8C 20                            ; O16 for 16-bit operand size
+       MOVl %cs,(%r8)                # --  --  -- 41   8C 08                            ; REX to access upper reg.
+       MOVl %cs,(%rax)               # --  --  -- --   8C 08
+       MOVl %ss,(%r8)                # --  --  -- 41   8C 10                            ; REX to access upper reg.
+       MOVl %ss,(%rax)               # --  --  -- --   8C 10
+       MOVl %fs,(%r8)                # --  --  -- 41   8C 20                            ; REX to access upper reg.
+       MOVl %fs,(%rax)               # --  --  -- --   8C 20
+       MOVl (%r8),%ss                # --  --  -- 41   8E 10                            ; REX to access upper reg.
+       MOVl (%rax),%ss               # --  --  -- --   8E 10
+       MOVl (%r8),%fs                # --  --  -- 41   8E 20                            ; REX to access upper reg.
+       MOVl (%rax),%fs               # --  --  -- --   8E 20
+       MOVb $0,(%r8)                 # --  --  -- 41   C6 00 00                         ; REX to access upper reg.
+       MOVb $0,(%rax)                # --  --  -- --   C6 00 00
+       MOVw $0x7000,(%r8)            # 66  --  -- --   41 C7 00 00 70                   ; O16 for 16-bit operand size
+       MOVw $0x7000,(%rax)           # 66  --  -- --   C7 00 00 70                      ; O16 for 16-bit operand size
+       MOVl $0x70000000,(%rax)       # --  --  -- --   C7 00 00 00 00 70
+       MOVb $0,(%r8)                 # --  --  -- 41   C6 00 00                         ; REX to access upper reg.
+       MOVb $0,(%rax)                # --  --  -- --   C6 00 00
+       MOVw $0x7000,(%r8)            # 66  --  -- 41   C7 00 00 70                      ; REX to access upper reg. O16 for 16-bit operand size
+       MOVw $0x7000,(%rax)           # 66  --  -- --   C7 00 00 70                      ; O16 for 16-bit operand size
+       MOVl $0x70000000,(%r8)        # --  --  -- 41   C7 00 00 00 00 70                ; REX to access upper reg.
+       MOVl $0x70000000,(%rax)       # --  --  -- --   C7 00 00 00 00 70
+                                       
+       # MOVNTI                        
+       MOVNTI %eax,(%r8)             # --  --  -- 41   0f c3 00                         ; REX to access upper reg.
+       MOVNTI %eax,(%rax)            # --  --  -- --   0f c3 00
+       MOVNTI %rax,(%r8)             # --  --  -- 49   0F C3 00                         ; REX to access upper reg. REX for 64-bit operand size
+       MOVNTI %rax,(%rax)            # --  --  -- 48   0F C3 00                         ; REX for 64-bit operand size. REX to access upper reg.
+       MOVNTI %r8,(%r8)              # --  --  -- 4D   0F C3 00                         ; REX to access upper reg. REX for 64-bit operand size
+       MOVNTI %r8,(%rax)             # --  --  -- 4C   0F C3 00                         ; REX to access upper reg. REX for 64-bit operand size
+
+       # Conditionals
+
+       # LOOP
+
+
+       # Jcc
+                                     #  66  --  -- --   77 FD                           ; A16 override: (Addr64) = ZEXT(Addr16)
+                                     #  66  --  -- --   0F 87 F9 FF FF FF               ; A16 override: (Addr64) = ZEXT(Addr16)
+
+       # J*CXZ
+                                     #  66  67  -- --   E3 FC                           ; ECX used as counter. A16 override: (Addr64) = ZEXT(Addr16)
+                                     #  66  --  -- --   E3 FD                           ; A16 override: (Addr64) = ZEXT(Addr16)
+
+
+
+       # Integer
+
+       # IDIV
+
+       IDIVb (%r8)                   #  --  --  -- 41   F6 38                           ; Sign extended result. REX to access upper reg.
+       IDIVb (%rax)                  #  --  --  -- --   F6 38                           ; Sign extended result
+       IDIVw (%r8)                   #  66  --  -- 41   F7 38                           ; Sign extended result. REX to access upper reg. O16 for 16-bit
+       IDIVw (%rax)                  #  66  --  -- --   F7 38                           ; Sign extended result. O16 for 16-bit operand size
+       IDIVl (%r8)                   #  --  --  -- 41   F7 38                           ; Sign extended result. REX to access upper reg
+       IDIVl (%rax)                  #  --  --  -- --   F7 38                           ; Sign extended result
+       IDIVq (%r8)                   #  --  --  -- 49   F7 38                           ; Sign extended result. REX for 64-bit operand size. REX to access u
+       IDIVq (%rax)                  #  --  --  -- 48   F7 38                           ; Sign extended result. REX for 64-bit operand size
+
+       # IMUL
+       IMULb (%r8)                   #  --  --  -- 41   F6 28                           ; Sign extended result. REX to access upper reg
+       IMULb (%rax)                  #  --  --  -- --   F6 28                           ; Sign extended result
+       IMULw (%r8)                   #  66  --  -- 41   F7 28                           ; Sign extended result. O16 for 16-bit operand size. REX to access
+       IMULw (%rax)                  #  66  --  -- --   F7 28                           ; Sign extended result. O16 for 16-bit operand size
+       IMULl (%r8)                   #  --  --  -- 41   F7 28                           ; Sign extended result. REX to access upper reg
+       IMULl (%rax)                  #  --  --  -- --   F7 28                           ; Sign extended result
+       IMULq (%r8)                   #  --  --  -- 49   F7 28                           ; Sign extended result. REX for 64-bit operand size. REX to access u
+       IMULq (%rax)                  #  --  --  -- 48   F7 28                           ; Sign extended result. REX for 64-bit operand size
+
+
+
+       # SIMD/SSE
+
+       # ADDPD
+       ADDPD  (%r8),%xmm0            #  --  --  66 41   0F 58 00                        ; REX to access upper reg. OVR 128bit MMinstr.
+       ADDPD  (%rax),%xmm0           #  --  --  66 --   0F 58 00                        ; OVR 128bit MMinstr.
+       ADDPD  (%r8),%xmm15           #  --  --  66 45   0F 58 38                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+       ADDPD  (%rax),%xmm15          #  --  --  66 44   0F 58 38                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       ADDPD  (%r8),%xmm8            #  --  --  66 45   0F 58 00                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+       ADDPD  (%rax),%xmm8           #  --  --  66 44   0F 58 00                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       ADDPD  (%r8),%xmm7            #  --  --  66 41   0F 58 38                        ; REX to access upper reg. OVR 128bit MMinstr.
+       ADDPD  (%rax),%xmm7           #  --  --  66 --   0F 58 38                        ; OVR 128bit MMinstr.
+       ADDPD  %xmm0,%xmm0            #  --  --  66 --   0F 58 C0                        ; OVR 128bit MMinstr.
+       ADDPD  %xmm15,%xmm15          #  --  --  66 45   0F 58 FF                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       ADDPD  %xmm15,%xmm8           #  --  --  66 45   0F 58 C7                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+
+       # CMPPD
+        
+        # CVTSD2SI                                       
+       CVTSD2SIq (%r8),%rax          #  --  --  F2 49   0f 2d 00                        ; OVR 128-bit media instruction override REX for 64-bit operand size                  REX to access upper reg.  
+       CVTSD2SIq (%rax),%rax         #  --  --  F2 48   0f 2d 00                        ; OVR 128-bit media instruction override REX for 64-bit operand size 
+       CVTSD2SIq (%r8),%r8           #  --  --  F2 4D   0f 2d 00                        ; OVR 128-bit media instruction override REX for 64-bit operand size                REX to access upper reg.  
+       CVTSD2SIq (%rax),%r8          #  --  --  F2 4C   0f 2d 00                        ; OVR 128-bit media instruction override REX for 64-bit operand size                  REX to access upper reg.  
+       CVTSD2SIq %xmm0,%rax          #  --  --  F2 48   0f 2d c0                        ; OVR 128-bit media instruction override REX for 64-bit operand size 
+       CVTSD2SIq %xmm15,%r8          #  --  --  F2 4D   0f 2d c7                        ; OVR 128-bit media instruction override REX for 64-bit operand size                 REX to access upper XMM reg             REX to access upper reg.  
+       CVTSD2SIq %xmm15,%rax         #  --  --  F2 49   0f 2d c7                        ; OVR 128-bit media instruction override REX for 64-bit operand size                  REX to access upper XMM reg
+       CVTSD2SIq %xmm8,%r8           #  --  --  F2 4D   0f 2d c0                        ; OVR 128-bit media instruction override REX for 64-bit operand size                  REX to access upper XMM reg             REX to access upper reg.  
+       CVTSD2SIq %xmm8,%rax          #  --  --  F2 49   0f 2d c0                        ; OVR 128-bit media instruction override REX for 64-bit operand size                  REX to access upper XMM reg
+       CVTSD2SIq %xmm7,%r8           #  --  --  F2 4C   0f 2d c7                        ; OVR 128-bit media instruction override REX for 64-bit operand size                 REX to access upper reg.  
+       CVTSD2SIq %xmm7,%rax          #  --  --  F2 48   0f 2d c7                        ; OVR 128-bit media instruction override REX for 64-bit operand size 
+       CVTSD2SIq %xmm0,%r8           #  --  --  F2 4C   0f 2d c0                        ; OVR 128-bit media instruction override REX for 64-bit operand size                  REX to access upper reg.  
+                                                               
+        # CVTTSD2SI                                      
+       CVTTSD2SIq (%r8),%rax         #  --  --  F2 49   0f 2c 00                        ; OVR 128-bit media instruction override REX for 64-bit operand size                REX to access upper reg.  
+       CVTTSD2SIq (%rax),%rax        #  --  --  F2 48   0f 2c 00                        ; OVR 128-bit media instruction override REX for 64-bit operand size 
+       CVTTSD2SIq (%r8),%r8          #  --  --  F2 4D   0f 2c 00                        ; OVR 128-bit media instruction override REX for 64-bit operand size                  REX to access upper reg.  
+       CVTTSD2SIq (%rax),%r8         #  --  --  F2 4C   0f 2c 00                        ; OVR 128-bit media instruction override REX for 64-bit operand size                   REX to access upper reg.  
+       CVTTSD2SIq %xmm0,%rax         #  --  --  F2 48   0f 2c c0                        ; OVR 128-bit media instruction override REX for 64-bit operand size 
+       CVTTSD2SIq %xmm15,%r8         #  --  --  F2 4D   0f 2c c7                        ; OVR 128-bit media instruction override REX for 64-bit operand size                 REX to access upper XMM reg             REX to access upper reg.  
+       CVTTSD2SIq %xmm15,%rax        #  --  --  F2 49   0f 2c c7                        ; OVR 128-bit media instruction override REX for 64-bit operand size                 REX to access upper XMM reg
+       CVTTSD2SIq %xmm8,%r8          #  --  --  F2 4D   0f 2c c0                        ; OVR 128-bit media instruction override REX for 64-bit operand size                 REX to access upper XMM reg             REX to access upper reg.  
+       CVTTSD2SIq %xmm8,%rax         #  --  --  F2 49   0f 2c c0                        ; OVR 128-bit media instruction override REX for 64-bit operand size                 REX to access upper XMM reg
+       CVTTSD2SIq %xmm7,%r8          #  --  --  F2 4C   0f 2c c7                        ; OVR 128-bit media instruction override REX for 64-bit operand size                  REX to access upper reg.  
+       CVTTSD2SIq %xmm7,%rax         #  --  --  F2 48   0f 2c c7                        ; OVR 128-bit media instruction override REX for 64-bit operand size 
+       CVTTSD2SIq %xmm0,%r8          #  --  --  F2 4C   0f 2c c0                        ; OVR 128-bit media instruction override REX for 64-bit operand size                 REX to access upper reg.  
+                                                        
+        # CVTSS2SI                                       
+       CVTSS2SIq (%r8),%rax          #  --  --  F3 49   0f 2d 00                        ; OVR 128-bit media instruction override Result is sign extended                         REX for 64-bit operand size                  REX to access upper reg.  
+       CVTSS2SIq (%rax),%rax         #  --  --  F3 48   0f 2d 00                        ; OVR 128-bit media instruction override Result is sign extended                       REX for 64-bit operand size 
+       CVTSS2SIq (%r8),%r8           #  --  --  F3 4D   0f 2d 00                        ; OVR 128-bit media instruction override Result is sign extended                        REX for 64-bit operand size                  REX to access upper reg.  
+       CVTSS2SIq (%rax),%r8          #  --  --  F3 4C   0f 2d 00                        ; OVR 128-bit media instruction override Result is sign extended                         REX for 64-bit operand size                 REX to access upper reg.  
+       CVTSS2SIq %xmm0,%rax          #  --  --  F3 48   0f 2d c0                        ; OVR 128-bit media instruction override Result is sign extended                       REX for 64-bit operand size 
+       CVTSS2SIq %xmm15,%r8          #  --  --  F3 4D   0f 2d c7                        ; OVR 128-bit media instruction override Result is sign extended                       REX to access upper XMM reg            REX to access upper reg.  
+       CVTSS2SIq %xmm15,%rax         #  --  --  F3 49   0f 2d c7                        ; OVR 128-bit media instruction override Result is sign extended                       REX for 64-bit operand size                 REX to access upper XMM reg
+       CVTSS2SIq %xmm8,%r8           #  --  --  F3 4D   0f 2d c0                        ; OVR 128-bit media instruction override Result is sign extended                          REX for 64-bit operand size                  REX to access upper XMM reg              REX to access upper reg.  
+       CVTSS2SIq %xmm8,%rax          #  --  --  F3 49   0f 2d c0                        ; OVR 128-bit media instruction override Result is sign extended                          REX for 64-bit operand size 
+       CVTSS2SIq %xmm7,%r8           #  --  --  F3 4C   0f 2d c7                        ; OVR 128-bit media instruction override Result is sign extended                       REX for 64-bit operand size                 REX to access upper reg.  
+       CVTSS2SIq %xmm7,%rax          #  --  --  F3 48   0f 2d c7                        ; OVR 128-bit media instruction override Result is sign extended                          REX for 64-bit operand size 
+       CVTSS2SIq %xmm0,%r8           #  --  --  F3 4C   0f 2d c0                        ; OVR 128-bit media instruction override Result is sign extended                       REX for 64-bit operand size                REX to access upper reg.  
+                                               
+        # CVTTSS2SI                                      
+       CVTTSS2SIq (%r8),%rax         #  --  --  F3 49   0f 2c 00                        ; OVR 128-bit media instruction override Result is sign extended                       REX for 64-bit operand size                  REX to access upper reg.  
+       CVTTSS2SIq (%rax),%rax        #  --  --  F3 48   0f 2c 00                        ; OVR 128-bit media instruction override Result is sign extended                        REX for 64-bit operand size 
+       CVTTSS2SIq (%r8),%r8          #  --  --  F3 4D   0f 2c 00                        ; OVR 128-bit media instruction override Result is sign extended                        REX for 64-bit operand size                   REX to access upper reg.  
+       CVTTSS2SIq (%rax),%r8         #  --  --  F3 4C   0f 2c 00                        ; OVR 128-bit media instruction override Result is sign extended                       REX for 64-bit operand size                    REX to access upper reg.  
+       CVTTSS2SIq %xmm0,%rax         #  --  --  F3 48   0f 2c c0                        ; OVR 128-bit media instruction override Result is sign extended                        REX for 64-bit operand size 
+       CVTTSS2SIq %xmm15,%r8         #  --  --  F3 4D   0f 2c c7                        ; OVR 128-bit media instruction override Result is sign extended                       REX for 64-bit operand size                 REX to access upper XMM reg            REX to access upper reg.  
+       CVTTSS2SIq %xmm15,%rax        #  --  --  F3 49   0f 2c c7                        ; OVR 128-bit media instruction override Result is sign extended                        REX for 64-bit operand size                 REX to access upper XMM reg
+       CVTTSS2SIq %xmm8,%r8          #  --  --  F3 4D   0f 2c c0                        ; OVR 128-bit media instruction override Result is sign extended                          REX for 64-bit operand size                  REX to access upper XMM reg               REX to access upper reg.  
+       CVTTSS2SIq %xmm8,%rax         #  --  --  F3 49   0f 2c c0                        ; OVR 128-bit media instruction override Result is sign extended                        REX for 64-bit operand size 
+       CVTTSS2SIq %xmm7,%r8          #  --  --  F3 4C   0f 2c c7                        ; OVR 128-bit media instruction override Result is sign extended                        REX for 64-bit operand size                 REX to access upper reg.  
+       CVTTSS2SIq %xmm7,%rax         #  --  --  F3 48   0f 2c c7                        ; OVR 128-bit media instruction override Result is sign extended
+       CVTTSS2SIq %xmm0,%r8          #  --  --  F3 4C   0f 2c c0                        ; OVR 128-bit media instruction override Result is sign extended                          REX for 64-bit operand size                 REX to access upper reg.  
+                                                
+        # CVTSI2SS                                       
+       CVTSI2SS  (%r8),%xmm0         #  --  --  F3 41   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper reg. 
+       CVTSI2SS  (%rax),%xmm0        #  --  --  F3 --   0f 2a 00                        ; OVR 128-bit media instruction override 
+       CVTSI2SS  (%r8),%xmm15        #  --  --  F3 45   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.  
+       CVTSI2SS  (%rax),%xmm15       #  --  --  F3 44   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper XMM reg
+       CVTSI2SS  (%r8),%xmm8         #  --  --  F3 45   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.  
+       CVTSI2SS  (%rax),%xmm8        #  --  --  F3 44   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper XMM reg
+       CVTSI2SS  (%r8),%xmm7         #  --  --  F3 41   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper reg. 
+       CVTSI2SS  (%rax),%xmm7        #  --  --  F3 --   0f 2a 38                        ; OVR 128-bit media instruction override 
+       CVTSI2SS  %eax,%xmm0          #  --  --  F3 --   0f 2a c0                        ; OVR 128-bit media instruction override 
+       CVTSI2SS  %eax,%xmm15         #  --  --  F3 44   0f 2a f8                        ; OVR 128-bit media instruction override REX to access upper XMM reg
+       CVTSI2SS  %eax,%xmm8          #  --  --  F3 44   0f 2a c0                        ; OVR 128-bit media instruction override REX to access upper XMM reg
+       CVTSI2SS  %eax,%xmm7          #  --  --  F3 --   0f 2a f8                        ; OVR 128-bit media instruction override 
+       CVTSI2SS  (%r8),%xmm0         #  --  --  F3 41   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper reg. 
+       CVTSI2SS  (%rax),%xmm0        #  --  --  F3 --   0f 2a 00                        ; OVR 128-bit media instruction override 
+       CVTSI2SS  (%r8),%xmm15        #  --  --  F3 45   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.  
+       CVTSI2SS  (%rax),%xmm15       #  --  --  F3 44   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper XMM reg
+       CVTSI2SS  (%r8),%xmm8         #  --  --  F3 45   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.  
+       CVTSI2SS  (%rax),%xmm8        #  --  --  F3 44   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper XMM reg
+       CVTSI2SS  (%r8),%xmm7         #  --  --  F3 41   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper reg. 
+       CVTSI2SS  (%rax),%xmm7        #  --  --  F3 --   0f 2a 38                        ; OVR 128-bit media instruction override 
+                                            
+        # CVTSI2SD
+       CVTSI2SD  (%r8),%xmm0         #  --  --  F2 41   0F 2A 00                        ; REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SD  (%rax),%xmm0        #  --  --  F2 --   0F 2A 00                        ; OVR 128bit MMinstr.
+       CVTSI2SD  (%r8),%xmm15        #  --  --  F2 45   0F 2A 38                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SD  (%rax),%xmm15       #  --  --  F2 44   0F 2A 38                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       CVTSI2SD  (%r8),%xmm8         #  --  --  F2 45   0F 2A 00                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SD  (%rax),%xmm8        #  --  --  F2 44   0F 2A 00                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       CVTSI2SD  (%r8),%xmm7         #  --  --  F2 41   0F 2A 38                        ; REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SD  (%rax),%xmm7        #  --  --  F2 --   0F 2A 38                        ; OVR 128bit MMinstr.
+       CVTSI2SD  %eax,%xmm0          #  --  --  F2 --   0F 2A C0                        ; OVR 128bit MMinstr.
+       CVTSI2SD  %eax,%xmm15         #  --  --  F2 44   0F 2A F8                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       CVTSI2SD  %eax,%xmm8          #  --  --  F2 44   0F 2A C0                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       CVTSI2SD  %eax,%xmm7          #  --  --  F2 --   0F 2A F8                        ; OVR 128bit MMinstr.
+       CVTSI2SD  (%r8),%xmm0         #  --  --  F2 41   0F 2A 00                        ; REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SD  (%rax),%xmm0        #  --  --  F2 --   0F 2A 00                        ; OVR 128bit MMinstr.
+       CVTSI2SD  (%r8),%xmm15        #  --  --  F2 45   0F 2A 38                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SD  (%rax),%xmm15       #  --  --  F2 44   0F 2A 38                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       CVTSI2SD  (%r8),%xmm8         #  --  --  F2 45   0F 2A 00                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SD  (%rax),%xmm8        #  --  --  F2 44   0F 2A 00                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       CVTSI2SD  (%r8),%xmm7         #  --  --  F2 41   0F 2A 38                        ; REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SD  (%rax),%xmm7        #  --  --  F2 --   0F 2A 38                        ; OVR 128bit MMinstr.
+
+       # MOVD
+       MOVD (%r8),%xmm0              #  --  --  66 41   0F 6E 00                        ; REX to access upper reg. Data128 = ZEXT(Data32). OVR 128bit MMinstr.
+       MOVD (%rax),%xmm0             #  --  --  66 --   0F 6E 00                        ; Data128 = ZEXT(Data32). OVR 128bit MMinstr.
+       MOVD (%r8),%xmm15             #  --  --  66 45   0F 6E 38                        ; REX to access upper XMM reg. REX to access upper reg. Data128 = ZEXT(Data32)
+       MOVD (%rax),%xmm15            #  --  --  66 44   0F 6E 38                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVD (%r8),%xmm8              #  --  --  66 45   0F 6E 00                        ; REX to access upper XMM reg. REX to access upper reg. Data128 = ZEXT(Data32)
+       MOVD (%rax),%xmm8             #  --  --  66 44   0F 6E 00                        ; REX to access upper XMM reg. Data128 = ZEXT(Data32). OVR 128bit MMinstr.
+       MOVD (%r8),%xmm7              #  --  --  66 41   0F 6E 38                        ; REX to access upper reg. Data128 = ZEXT(Data32). OVR 128bit MMinstr.
+       MOVD (%rax),%xmm7             #  --  --  66 --   0F 6E 38                        ; Data128 = ZEXT(Data32). OVR 128bit MMinstr.
+       MOVD %eax,%xmm0               #  --  --  66 --   0F 6E C0                        ; Data128 = ZEXT(Data32). OVR 128bit MMinstr.
+       MOVD %eax,%xmm15              #  --  --  66 44   0F 6E F8                        ; REX to access upper XMM reg. Data128 = ZEXT(Data32). OVR 128bit MMinstr.
+       MOVD %eax,%xmm8               #  --  --  66 44   0F 6E C0                        ; REX to access upper XMM reg. Data128 = ZEXT(Data32). OVR 128bit MMinstr.
+       MOVD %eax,%xmm7               #  --  --  66 --   0F 6E F8                        ; Data128 = ZEXT(Data32). OVR 128bit MMinstr.
+       MOVD %xmm0,(%r8)              #  --  --  66 41   0F 7E 00                        ; REX to access upper reg. OVR 128bit MMinstr.
+       MOVD %xmm0,(%rax)             #  --  --  66 --   0F 7E 00                        ; OVR 128bit MMinstr.
+       MOVD %xmm15,(%r8)             #  --  --  66 45   0F 7E 38                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+       MOVD %xmm15,(%rax)            #  --  --  66 44   0F 7E 38                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVD %xmm8,(%r8)              #  --  --  66 45   0F 7E 00                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+       MOVD %xmm8,(%rax)             #  --  --  66 44   0F 7E 00                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVD %xmm7,(%r8)              #  --  --  66 41   0F 7E 38                        ; REX to access upper reg. OVR 128bit MMinstr.
+       MOVD %xmm7,(%rax)             #  --  --  66 --   0F 7E 38                        ; OVR 128bit MMinstr.
+       MOVD %xmm0,%eax               #  --  --  66 --   0F 7E C0                        ; OVR 128bit MMinstr.
+       MOVD %xmm15,%eax              #  --  --  66 44   0F 7E F8                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVD %xmm8,%eax               #  --  --  66 44   0F 7E C0                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVD %xmm7,%eax               #  --  --  66 --   0F 7E F8                        ; OVR 128bit MMinstr.
+
+       # MOVQ
+       MOVQ (%r8),%xmm0              #  --  --  F3 41   0F 7E 00                        ; REX to access upper reg. Data128 = ZEXT(Data64). OVR 128bit MMinstr.
+       MOVQ (%rax),%xmm0             #  --  --  F3 --   0F 7E 00                        ; Data128 = ZEXT(Data64). OVR 128bit MMinstr.
+       MOVQ (%r8),%xmm15             #  --  --  F3 45   0F 7E 38                        ; REX to access upper XMM reg. REX to access upper reg. Data128 = ZEXT(Data64)
+       MOVQ (%rax),%xmm15            #  --  --  F3 44   0F 7E 38                        ; REX to access upper XMM reg. Data128 = ZEXT(Data64). OVR 128bit MMinstr.
+       MOVQ (%r8),%xmm8              #  --  --  F3 45   0F 7E 00                        ; REX to access upper XMM reg. REX to access upper reg. Data128 = ZEXT(Data64)
+       MOVQ (%rax),%xmm8             #  --  --  F3 44   0F 7E 00                        ; REX to access upper XMM reg. Data128 = ZEXT(Data64). OVR 128bit MMinstr.
+       MOVQ (%r8),%xmm7              #  --  --  F3 41   0F 7E 38                        ; REX to access upper reg. Data128 = ZEXT(Data64). OVR 128bit MMinstr.
+       MOVQ (%rax),%xmm7             #  --  --  F3 --   0F 7E 38                        ; Data128 = ZEXT(Data64). OVR 128bit MMinstr.
+       MOVQ %xmm0,%xmm0              #  --  --  F3 --   0F 7E C0                        ; OVR 128bit MMinstr.
+       MOVQ %xmm15,%xmm15            #  --  --  F3 45   0F 7E FF                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVQ %xmm15,%xmm8             #  --  --  F3 45   0F 7E C7                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVQ %xmm15,%xmm7             #  --  --  F3 41   0F 7E FF                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVQ %xmm15,%xmm0             #  --  --  F3 41   0F 7E C7                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVQ %xmm8,%xmm15             #  --  --  F3 45   0F 7E F8                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVQ %xmm8,%xmm8              #  --  --  F3 45   0F 7E C0                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVQ %xmm8,%xmm7              #  --  --  F3 41   0F 7E F8                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVQ %xmm8,%xmm0              #  --  --  F3 41   0F 7E C0                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVQ %xmm7,%xmm15             #  --  --  F3 44   0F 7E FF                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVQ %xmm7,%xmm8              #  --  --  F3 44   0F 7E C7                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVQ %xmm7,%xmm7              #  --  --  F3 --   0F 7E FF                        ; OVR 128bit MMinstr.
+       MOVQ %xmm7,%xmm0              #  --  --  F3 --   0F 7E C7                        ; OVR 128bit MMinstr.
+       MOVQ %xmm0,%xmm15             #  --  --  F3 44   0F 7E F8                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVQ %xmm0,%xmm8              #  --  --  F3 44   0F 7E C0                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVQ %xmm0,%xmm7              #  --  --  F3 --   0F 7E F8                        ; OVR 128bit MMinstr.
+       MOVQ %xmm0,(%r8)              #  --  --  66 41   0F D6 00                        ; REX to access upper reg. OVR 128bit MMinstr.
+       MOVQ %xmm0,(%rax)             #  --  --  66 --   0F D6 00                        ; OVR 128bit MMinstr.
+       MOVQ %xmm15,(%r8)             #  --  --  66 45   0F D6 38                        ; REX to access upper reg. OVR 128bit MMinstr.
+       MOVQ %xmm15,(%rax)            #  --  --  66 44   0F D6 38                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVQ %xmm8,(%r8)              #  --  --  66 45   0F D6 00                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+       MOVQ %xmm8,(%rax)             #  --  --  66 44   0F D6 00                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       MOVQ %xmm7,(%r8)              #  --  --  66 41   0F D6 38                        ; REX to access upper reg. OVR 128bit MMinstr.
+
+       # 64-bit MMX
+
+       # CVTPD2PI
+
+       # MOVD
+       MOVD (%r8),%mm0               #  --  --  -- 41   0F 6E 00                        ; REX to access upper reg. Data64 = ZEXT(Data32)
+       MOVD (%rax),%mm0              #  --  --  -- --   0F 6E 00                        ; Data64 = ZEXT(Data32)
+       MOVD (%r8),%mm7               #  --  --  -- 41   0F 6E 38                        ; REX to access upper reg. Data64 = ZEXT(Data32)
+       MOVD (%rax),%mm7              #  --  --  -- --   0F 6E 38                        ; Data64 = ZEXT(Data32)
+       MOVD %eax,%mm0                #  --  --  -- --   0F 6E C0                        ; Data64 = ZEXT(Data32)
+       MOVD %eax,%mm7                #  --  --  -- --   0F 6E F8                        ; Data64 = ZEXT(Data32)
+       MOVD %mm0,(%r8)               #  --  --  -- 41   0F 7E 00                        ; REX to access upper reg.
+       MOVD %mm0,(%rax)              #  --  --  -- --   0F 7E 00
+       MOVD %mm7,(%r8)               #  --  --  -- 41   0F 7E 38                        ; REX to access upper reg.
+       MOVD %mm7,(%rax)              #  --  --  -- --   0F 7E 38
+       MOVD %mm0,%eax                #  --  --  -- --   0F 7E C0
+       MOVD %mm7,%eax                #  --  --  -- --   0F 7E F8
+
+       # MOVQ
+       MOVQ (%r8),%mm0               #  --  --  -- 41   0F 6F 00                        ; REX to access upper reg.
+       MOVQ (%rax),%mm0              #  --  --  -- --   0F 6F 00
+       MOVQ (%r8),%mm7               #  --  --  -- 41   0F 6F 38                        ; REX to access upper reg.
+       MOVQ (%rax),%mm7              #  --  --  -- --   0F 6F 38
+       MOVQ %mm0,(%r8)               #  --  --  -- 41   0F 7F 00                        ; REX to access upper reg.
+       MOVQ %mm0,(%rax)              #  --  --  -- --   0F 7F 00
+       MOVQ %mm7,(%r8)               #  --  --  -- 41   0F 7F 38                        ; REX to access upper reg.
+       MOVQ %mm7,(%rax)              #  --  --  -- --   0F 7F 38
+
+       # X87
+       # FADDP
+
+
+       # FDIV
+
+       # Stack Operations
+
+       # POP
+       POPq (%r8)                    #  --  --  -- 41   8F 00                           ; REX to access upper reg.
+       POPq (%rax)                   #  --  --  -- --   8F 00
+       POPFQ                         #  --  --  -- --   9D
+
+       # PUSH
+       PUSHq (%r8)                   #  --  --  -- 41   FF 30                           ; REX to access upper reg.
+       PUSHq (%rax)                  #  --  --  -- --   FF 30
+       PUSHFQ                        #  --  --  -- --   9C
+
+
+
+
+
+       # MMX/XMM/x87 State
+       # FNSAVE
+       # FRSTOR
+       # FSAVE
+       # FXRSTOR
+       # FXSAVE
+       # EMMS
+       EMMS                          #  --  --  -- --   0F 77
+       # FEMMS
+       FEMMS                         #  --  --  -- --   0F 0E
+
+       # LEA calculation
+
+       # MISC System Instructions
+       # CLFLUSH
+
+       # INVD
+       INVD                          #  --  --  -- --   0F 08
+
+       # INVLPG
+       INVLPG (%r8)                  #  --  --  -- 41   0F 01 38                        ; REX to access upper reg.
+       INVLPG (%rax)                 #  --  --  -- --   0F 01 38
+       INVLPG (%r8)                  #  --  --  -- 41   0F 01 38                        ; REX to access upper reg.
+       INVLPG (%rax)                 #  --  --  -- --   0F 01 38
+       INVLPG (%r8)                  #  --  --  -- 41   0F 01 38                        ; REX to access upper reg.
+       INVLPG (%rax)                 #  --  --  -- --   0F 01 38
+
+       # LAR
+
+       # LGDT
+
+       # LIDT
+
+
+       # LLDT
+
+       # SGDT
+
+       # SIDT
+
+       # SLDT
+#        SLDT (%eax)                 #  --  67  -- --   0F 00 00                        ; A32 override: (Addr64) = ZEXT(Addr32 )
+        SLDT %eax                    #  --  --  -- --   0F 00 C0       
+
+       # SWAPGS
+
+
+
+       # IO
+
+       # OUT
+       OUT %al,$0                    #  --  --  -- --   E6 00
+       OUT %ax,$0                    #  66  --  -- --   E7 00                           ; O16 for 16-bit operand size
+       OUT %eax,$0                   #  --  --  -- --   E7 00
+
+       # IN