The tgsi path already marked all aliasing loads of atomic counters with
CACHE_CG, so we don't need to emit a cctl. This patch uses the cache
flag on the atomic to model whether the L1 cache needs the stale
values to be flushed or not.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14386>
if (ind)
insn->setIndirect(0, 1, ind);
insn->subOp = subOp;
+
+ if (tgsi.getSrc(0).getFile() == TGSI_FILE_BUFFER &&
+ code->bufferAtomics[tgsi.getSrc(0).getIndex(0)])
+ insn->cache = nv50_ir::CACHE_CG;
}
for (int c = 0; c < 4; ++c)
if (dst0[c])
NVC0LoweringPass::handleATOMCctl(Instruction *atom) {
// Flush L1 cache manually since atomics go directly to L2. This ensures
// that any later CA reads retrieve the updated data.
+
+ if (atom->cache != nv50_ir::CACHE_CA)
+ return false;
+
bld.setPosition(atom, true);
Instruction *cctl = bld.mkOp1(OP_CCTL, TYPE_NONE, NULL, atom->getSrc(0));