Update PCI IDs for Haswell CRW

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

diff --git a/src/intel_driver.h b/src/intel_driver.h
index 1e30f23..e3e3f5d 100644 (file)
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -202,15 +202,15 @@ struct intel_region
 #define        PCI_CHIP_HASWELL_ULT_S_GT2              0x0A1A
 #define        PCI_CHIP_HASWELL_ULT_S_GT2_PLUS         0x0A2A
 
-#define        PCI_CHIP_HASWELL_CRW_GT1                0x0D12 /* Desktop */
-#define        PCI_CHIP_HASWELL_CRW_GT2                0x0D22
-#define        PCI_CHIP_HASWELL_CRW_GT2_PLUS           0x0D32
-#define        PCI_CHIP_HASWELL_CRW_M_GT1              0x0D16 /* Mobile */
-#define        PCI_CHIP_HASWELL_CRW_M_GT2              0x0D26
-#define        PCI_CHIP_HASWELL_CRW_M_GT2_PLUS         0x0D36
-#define        PCI_CHIP_HASWELL_CRW_S_GT1              0x0D1A /* Server */
-#define        PCI_CHIP_HASWELL_CRW_S_GT2              0x0D2A
-#define        PCI_CHIP_HASWELL_CRW_S_GT2_PLUS         0x0D3A
+#define        PCI_CHIP_HASWELL_CRW_GT1                0x0D02 /* Desktop */
+#define        PCI_CHIP_HASWELL_CRW_GT2                0x0D12
+#define        PCI_CHIP_HASWELL_CRW_GT2_PLUS           0x0D22
+#define        PCI_CHIP_HASWELL_CRW_M_GT1              0x0D06 /* Mobile */
+#define        PCI_CHIP_HASWELL_CRW_M_GT2              0x0D16
+#define        PCI_CHIP_HASWELL_CRW_M_GT2_PLUS         0x0D26
+#define        PCI_CHIP_HASWELL_CRW_S_GT1              0x0D0A /* Server */
+#define        PCI_CHIP_HASWELL_CRW_S_GT2              0x0D1A
+#define        PCI_CHIP_HASWELL_CRW_S_GT2_PLUS         0x0D2A
 
 #define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G ||   \
                                  devid == PCI_CHIP_Q45_G ||     \