ir3: Make instruction IP 32 bits

a6xx supports shaders with more than 64k dwords, or at least the shader
size register has increased in size, and the matching name is gone so
there's no reason to be clever here. This doesn't fix anything at the
moment.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12487>

diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h
index 759be5f21ff4cbfe73615ef4f4624fa9716b8759..9d8f09b3bb5bc7a4e4cf2ebd9c46fc9ddb33de2d 100644 (file)
--- a/src/freedreno/ir3/ir3.h
+++ b/src/freedreno/ir3/ir3.h
@@ -384,7 +384,7 @@ struct ir3_instruction {
    };
 
    /* For assigning jump offsets, we need instruction's position: */
-   uint16_t ip;
+   uint32_t ip;
 
    /* used for per-pass extra instruction data.
     *