media: hantro: add initial SAMA5D4 support

The SoC features a Hantro G1 compatible video decoder, supporting the
MPEG-2, VP8 and H264 codecs with resolutions up-to 1280x720.

Post-processing core is also available on the SoC.

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig
index 5b6cf9f..20b1f6d 100644 (file)
--- a/drivers/staging/media/hantro/Kconfig
+++ b/drivers/staging/media/hantro/Kconfig
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 config VIDEO_HANTRO
        tristate "Hantro VPU driver"
-       depends on ARCH_MXC || ARCH_ROCKCHIP || COMPILE_TEST
+       depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || COMPILE_TEST
        depends on VIDEO_DEV && VIDEO_V4L2
        select MEDIA_CONTROLLER
        select MEDIA_CONTROLLER_REQUEST_API
@@ -24,6 +24,14 @@ config VIDEO_HANTRO_IMX8M
        help
          Enable support for i.MX8M SoCs.
 
+config VIDEO_HANTRO_SAMA5D4
+       bool "Hantro VDEC SAMA5D4 support"
+       depends on VIDEO_HANTRO
+       depends on ARCH_AT91 || COMPILE_TEST
+       default y
+       help
+         Enable support for Microchip SAMA5D4 SoCs.
+
 config VIDEO_HANTRO_ROCKCHIP
        bool "Hantro VPU Rockchip support"
        depends on VIDEO_HANTRO

diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile
index 3747a32..f4b9990 100644 (file)
--- a/drivers/staging/media/hantro/Makefile
+++ b/drivers/staging/media/hantro/Makefile
@@ -22,6 +22,9 @@ hantro-vpu-y += \
 hantro-vpu-$(CONFIG_VIDEO_HANTRO_IMX8M) += \
                imx8m_vpu_hw.o
 
+hantro-vpu-$(CONFIG_VIDEO_HANTRO_SAMA5D4) += \
+               sama5d4_vdec_hw.o
+
 hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \
                rk3288_vpu_hw.o \
                rk3399_vpu_hw.o

diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
index dd37d87..85dcb08 100644 (file)
--- a/drivers/staging/media/hantro/hantro_drv.c
+++ b/drivers/staging/media/hantro/hantro_drv.c
@@ -490,6 +490,9 @@ static const struct of_device_id of_hantro_match[] = {
 #ifdef CONFIG_VIDEO_HANTRO_IMX8M
        { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
 #endif
+#ifdef CONFIG_VIDEO_HANTRO_SAMA5D4
+       { .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, },
+#endif
        { /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, of_hantro_match);

diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
index a1008e5..0a42df2 100644 (file)
--- a/drivers/staging/media/hantro/hantro_hw.h
+++ b/drivers/staging/media/hantro/hantro_hw.h
@@ -164,6 +164,7 @@ extern const struct hantro_variant rk3399_vpu_variant;
 extern const struct hantro_variant rk3328_vpu_variant;
 extern const struct hantro_variant rk3288_vpu_variant;
 extern const struct hantro_variant imx8mq_vpu_variant;
+extern const struct hantro_variant sama5d4_vdec_variant;
 
 extern const struct hantro_postproc_regs hantro_g1_postproc_regs;
 

diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c
new file mode 100644 (file)
index 0000000..58ae72c
--- /dev/null
+++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Hantro VDEC driver
+ *
+ * Copyright (C) 2021 Collabora Ltd, Emil Velikov <emil.velikov@collabora.com>
+ */
+
+#include "hantro.h"
+
+/*
+ * Supported formats.
+ */
+
+static const struct hantro_fmt sama5d4_vdec_postproc_fmts[] = {
+       {
+               .fourcc = V4L2_PIX_FMT_YUYV,
+               .codec_mode = HANTRO_MODE_NONE,
+       },
+};
+
+static const struct hantro_fmt sama5d4_vdec_fmts[] = {
+       {
+               .fourcc = V4L2_PIX_FMT_NV12,
+               .codec_mode = HANTRO_MODE_NONE,
+       },
+       {
+               .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
+               .codec_mode = HANTRO_MODE_MPEG2_DEC,
+               .max_depth = 2,
+               .frmsize = {
+                       .min_width = 48,
+                       .max_width = 1280,
+                       .step_width = MB_DIM,
+                       .min_height = 48,
+                       .max_height = 720,
+                       .step_height = MB_DIM,
+               },
+       },
+       {
+               .fourcc = V4L2_PIX_FMT_VP8_FRAME,
+               .codec_mode = HANTRO_MODE_VP8_DEC,
+               .max_depth = 2,
+               .frmsize = {
+                       .min_width = 48,
+                       .max_width = 1280,
+                       .step_width = MB_DIM,
+                       .min_height = 48,
+                       .max_height = 720,
+                       .step_height = MB_DIM,
+               },
+       },
+       {
+               .fourcc = V4L2_PIX_FMT_H264_SLICE,
+               .codec_mode = HANTRO_MODE_H264_DEC,
+               .max_depth = 2,
+               .frmsize = {
+                       .min_width = 48,
+                       .max_width = 1280,
+                       .step_width = MB_DIM,
+                       .min_height = 48,
+                       .max_height = 720,
+                       .step_height = MB_DIM,
+               },
+       },
+};
+
+static int sama5d4_hw_init(struct hantro_dev *vpu)
+{
+       return 0;
+}
+
+/*
+ * Supported codec ops.
+ */
+
+static const struct hantro_codec_ops sama5d4_vdec_codec_ops[] = {
+       [HANTRO_MODE_MPEG2_DEC] = {
+               .run = hantro_g1_mpeg2_dec_run,
+               .reset = hantro_g1_reset,
+               .init = hantro_mpeg2_dec_init,
+               .exit = hantro_mpeg2_dec_exit,
+       },
+       [HANTRO_MODE_VP8_DEC] = {
+               .run = hantro_g1_vp8_dec_run,
+               .reset = hantro_g1_reset,
+               .init = hantro_vp8_dec_init,
+               .exit = hantro_vp8_dec_exit,
+       },
+       [HANTRO_MODE_H264_DEC] = {
+               .run = hantro_g1_h264_dec_run,
+               .reset = hantro_g1_reset,
+               .init = hantro_h264_dec_init,
+               .exit = hantro_h264_dec_exit,
+       },
+};
+
+static const struct hantro_irq sama5d4_irqs[] = {
+       { "vdec", hantro_g1_irq },
+};
+
+static const char * const sama5d4_clk_names[] = { "vdec_clk" };
+
+const struct hantro_variant sama5d4_vdec_variant = {
+       .dec_fmts = sama5d4_vdec_fmts,
+       .num_dec_fmts = ARRAY_SIZE(sama5d4_vdec_fmts),
+       .postproc_fmts = sama5d4_vdec_postproc_fmts,
+       .num_postproc_fmts = ARRAY_SIZE(sama5d4_vdec_postproc_fmts),
+       .postproc_regs = &hantro_g1_postproc_regs,
+       .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
+                HANTRO_H264_DECODER,
+       .codec_ops = sama5d4_vdec_codec_ops,
+       .init = sama5d4_hw_init,
+       .irqs = sama5d4_irqs,
+       .num_irqs = ARRAY_SIZE(sama5d4_irqs),
+       .clk_names = sama5d4_clk_names,
+       .num_clocks = ARRAY_SIZE(sama5d4_clk_names),
+};