arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106
authorMichal Simek <michal.simek@xilinx.com>
Thu, 21 Jan 2021 10:26:50 +0000 (11:26 +0100)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 1 Feb 2021 09:36:07 +0000 (10:36 +0100)
Origin DT binding just specify driver but wasn't aligned with DT binding
which came later. Extend description for zcu102 and zcu106 to cover latest
binding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/82b2b13006307f108ace81c50c213c3857078b57.1611224800.git.michal.simek@xilinx.com
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts

index f1255f635dfd7c898104d2d92c6c157681a7f19e..5ff7ab6653743acc892e4bf8278d1a1cb20a4bd6 100644 (file)
                compatible = "iio-hwmon";
                io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
        };
+
+       refhdmi: refhdmi {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <114285000>;
+       };
 };
 
 &can1 {
                                 * interrupt-parent = <&>;
                                 * interrupts = <>;
                                 */
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               #clock-cells = <1>;
+                               clocks = <&refhdmi>;
+                               clock-names = "xtal";
+                               clock-output-names = "si5328";
+
+                               si5328_clk: clk0@0 {
+                                       reg = <0>;
+                                       clock-frequency = <27000000>;
+                               };
                        };
                };
                /* 5 - 7 unconnected */
index 6e9efe2338388b8950c50afbc08cec069b164872..7910ac1251011efe4d2b93828a73b5a0cf7e544f 100644 (file)
                compatible = "iio-hwmon";
                io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
        };
+
+       refhdmi: refhdmi {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <114285000>;
+       };
 };
 
 &can1 {
                        reg = <4>;
                        si5328: clock-generator@69 {/* SI5328 - u20 */
                                reg = <0x69>;
+                               /*
+                                * Chip has interrupt present connected to PL
+                                * interrupt-parent = <&>;
+                                * interrupts = <>;
+                                */
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               #clock-cells = <1>;
+                               clocks = <&refhdmi>;
+                               clock-names = "xtal";
+                               clock-output-names = "si5328";
+
+                               si5328_clk: clk0@0 {
+                                       reg = <0>;
+                                       clock-frequency = <27000000>;
+                               };
                        };
                };
                i2c@5 {