ddr: fsl: Remove CONFIG_MEM_INIT_VALUE

The way all of the memory init code here works is that we pass
0xDEADBEEF around for the initial value (as it's a well known 'poison'
value and so easily recognized in debuggers, etc). The only point of
this CONFIG symbol was to pass in a different value for that purpose.
Drop this symbol and cleanup the code slightly.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/powerpc/include/asm/fsl_dma.h b/arch/powerpc/include/asm/fsl_dma.h
index 727f4a7..1459db7 100644 (file)
--- a/arch/powerpc/include/asm/fsl_dma.h
+++ b/arch/powerpc/include/asm/fsl_dma.h
@@ -117,7 +117,7 @@ typedef struct fsl_dma {
 void dma_init(void);
 int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
 #if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
-void dma_meminit(uint val, uint size);
+void dma_meminit(uint size);
 #endif
 #endif
 

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index df7ec48..759921b 100644 (file)
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -938,7 +938,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
        /* Use the DDR controller to auto initialize memory. */
        d_init = popts->ecc_init_using_memctl;
-       ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
+       ddr->ddr_data_init = 0xDEADBEEF;
        debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 #else
        /* Memory will be initialized via DMA, or not at all. */
@@ -1842,19 +1842,6 @@ static void set_ddr_sdram_mode(const unsigned int ctrl_num,
 }
 #endif
 
-/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
-static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
-{
-       unsigned int init_value;        /* Initialization value */
-
-#ifdef CONFIG_MEM_INIT_VALUE
-       init_value = CONFIG_MEM_INIT_VALUE;
-#else
-       init_value = 0xDEADBEEF;
-#endif
-       ddr->ddr_data_init = init_value;
-}
-
 /*
  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
  * The old controller on the 8540/60 doesn't have this register.
@@ -2537,7 +2524,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
        set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm);
 
        set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
-       set_ddr_data_init(ddr);
+       ddr->ddr_data_init = 0xDEADBEEF;
        set_ddr_sdram_clk_cntl(ddr, popts);
        set_ddr_init_addr(ddr);
        set_ddr_init_ext_addr(ddr);

diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
index 0f1e99e..16186bd 100644 (file)
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -73,7 +73,7 @@ ddr_enable_ecc(unsigned int dram_size)
        struct ccsr_ddr __iomem *ddr =
                (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
 
-       dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
+       dma_meminit(dram_size);
 
        /*
         * Enable errors for ECC.

diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index cd78e45..700df22 100644 (file)
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -133,7 +133,7 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
  */
 #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) &&    \
        !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)))
-void dma_meminit(uint val, uint size)
+void dma_meminit(uint size)
 {
        uint *p = 0;
        uint i = 0;
@@ -142,7 +142,7 @@ void dma_meminit(uint val, uint size)
                if (((uint)p & 0x1f) == 0)
                        ppcDcbz((ulong)p);
 
-               *p = (uint)CONFIG_MEM_INIT_VALUE;
+               *p = (uint)0xDEADBEEF;
 
                if (((uint)p & 0x1c) == 0x1c)
                        ppcDcbf((ulong)p);

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 3d0c219..1e3ba6d 100644 (file)
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -26,8 +26,6 @@
 
 /* DDR Setup */
 
-#define CONFIG_MEM_INIT_VALUE  0xDeadBeef
-
 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000      /* DDR is system memory*/
 #define CFG_SYS_SDRAM_BASE             CFG_SYS_DDR_SDRAM_BASE
 

diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index c398ece..2267a7a 100644 (file)
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -98,8 +98,6 @@
 /* DDR Setup */
 #define SPD_EEPROM_ADDRESS             0x52
 
-#define CONFIG_MEM_INIT_VALUE          0xDeadBeef
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_sdram_size(void);
 #endif

diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 4b443c7..4794c5a 100644 (file)
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -94,9 +94,6 @@
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CFG_SYS_INIT_L2CSR0            L2CSR0_L2E
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
-#endif
 
 /*
  *  Config the L3 Cache as L3 SRAM

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index dfad76e..5bdc210 100644 (file)
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -64,9 +64,6 @@
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CFG_SYS_INIT_L2CSR0            L2CSR0_L2E
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
-#endif
 
 /*
  *  Config the L3 Cache as L3 SRAM

diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 24c1daf..4b6bdaa 100644 (file)
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -60,13 +60,6 @@
 #endif
 
 /*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
-#endif
-
-/*
  * Config the L3 Cache as L3 SRAM
  */
 #define CFG_SYS_INIT_L3_ADDR           0xFFFC0000

diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index c825e7f..fab40f7 100644 (file)
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -60,13 +60,6 @@
 #endif
 
 /*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
-#endif
-
-/*
  * Config the L3 Cache as L3 SRAM
  */
 #define CFG_SYS_INIT_L3_ADDR           0xFFFC0000

diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 95735f3..41565f2 100644 (file)
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -41,13 +41,6 @@
 #define CFG_SYS_NUM_CPC                CONFIG_SYS_NUM_DDR_CTLRS
 
 /*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
-#endif
-
-/*
  *  Config the L3 Cache as L3 SRAM
  */
 #define CFG_SYS_INIT_L3_ADDR           0xFFFC0000

diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h
index f7bb97a..a073a06 100644 (file)
--- a/include/configs/kontron_sl28.h
+++ b/include/configs/kontron_sl28.h
@@ -15,9 +15,6 @@
 #undef CFG_SYS_MEM_RESERVE_SECURE
 #endif
 
-/* DDR */
-#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
-
 #define CFG_SYS_DDR_SDRAM_BASE 0x80000000
 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
 #define CFG_SYS_SDRAM_BASE             CFG_SYS_DDR_SDRAM_BASE

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index e495884..fead9ed 100644 (file)
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -22,10 +22,6 @@
 #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
 #define CFG_SYS_SDRAM_BASE             CFG_SYS_DDR_SDRAM_BASE
 
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
-#endif
-
 /*
  * IFC Definitions
  */

diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 1dca7f0..7ccbb20 100644 (file)
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -12,10 +12,6 @@
 
 #define SPD_EEPROM_ADDRESS             0x51
 
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
-#endif
-
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define RGMII_PHY1_ADDR                0x1
 #define RGMII_PHY2_ADDR                0x2

diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 0439041..c8a6f01 100644 (file)
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -9,12 +9,6 @@
 
 #include "ls1043a_common.h"
 
-/* Physical Memory Map */
-
-#ifndef CONFIG_SPL
-#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
-#endif
-
 /*
  * NOR Flash Definitions
  */

diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index c4e5f49..4b4bd7c 100644 (file)
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -12,10 +12,6 @@
 
 #define SPD_EEPROM_ADDRESS             0x51
 
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
-#endif
-
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define RGMII_PHY1_ADDR                0x1
 #define RGMII_PHY2_ADDR                0x2

diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index ad766b0..0e42a51 100644 (file)
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -13,8 +13,6 @@
 
 #define SPD_EEPROM_ADDRESS             0x51
 
-#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
-
 #if defined(CONFIG_QSPI_BOOT)
 #define CFG_SYS_UBOOT_BASE             0x40100000
 #endif

diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 49ad146..3391540 100644 (file)
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -14,7 +14,6 @@
 
 #define COUNTER_FREQUENCY_REAL         (get_board_sys_clk()/4)
 
-#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 #define SPD_EEPROM_ADDRESS             0x51
 
 

diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index 9033f6e..1ddf068 100644 (file)
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -15,7 +15,6 @@
 
 #define COUNTER_FREQUENCY_REAL         25000000        /* 25MHz */
 
-#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #define SPD_EEPROM_ADDRESS     0x51
 
 

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 7d3e891..4a52fcd 100644 (file)
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -16,7 +16,6 @@
 #define CFG_SYS_I2C_FPGA_ADDR  0x66
 #define COUNTER_FREQUENCY_REAL         (get_board_sys_clk()/4)
 
-#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #define SPD_EEPROM_ADDRESS1    0x51
 #define SPD_EEPROM_ADDRESS2    0x52
 #define SPD_EEPROM_ADDRESS3    0x53

diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 4573906..b8ab501 100644 (file)
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -21,7 +21,6 @@
 
 #define COUNTER_FREQUENCY_REAL         (get_board_sys_clk()/4)
 
-#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #define SPD_EEPROM_ADDRESS1    0x51
 #define SPD_EEPROM_ADDRESS2    0x52
 #define SPD_EEPROM_ADDRESS3    0x53

diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 3347920..c1a98fd 100644 (file)
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -18,7 +18,6 @@
 #define CFG_SYS_DDR_BLOCK2_BASE                0x2080000000ULL
 #define CFG_SYS_SDRAM_SIZE                     0x200000000UL
 #define CFG_SYS_SDRAM_BASE             CFG_SYS_DDR_SDRAM_BASE
-#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #define SPD_EEPROM_ADDRESS1            0x51
 #define SPD_EEPROM_ADDRESS2            0x52
 #define SPD_EEPROM_ADDRESS3            0x53

diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 0547ed0..4c75209 100644 (file)
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -42,9 +42,6 @@
 #define CFG_SYS_CCSRBAR_PHYS_LOW       CFG_SYS_CCSRBAR
 
 /* DDR Setup */
-
-#define CONFIG_MEM_INIT_VALUE  0xDeadBeef
-
 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000
 #define CFG_SYS_SDRAM_BASE             CFG_SYS_DDR_SDRAM_BASE