* arm/ieee754-sf.S: Tidy formatting.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@71941 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1a505c1..708641a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,19 +1,23 @@
-2003-09-30  Nicolas Pitre <nico@cam.org>
+2003-09-30  Richard Earnshaw  <rearnsha@arm.com>
 
-       * arm/lib1funcs.asm (ARM_DIV_MOD_BODY) split into ARM_DIV_BODY
+       * arm/ieee754-sf.S: Tidy formatting.
+
+2003-09-30  Nicolas Pitre  <nico@cam.org>
+
+       * arm/lib1funcs.asm (ARM_DIV_MOD_BODY): Split into ARM_DIV_BODY
        and ARM_MOD_BODY.
-       (ARM_MOD_BODY): rewritten. added clz insns for __ARM_ARCH__ >= 5.
-       (ARM_DIV_BODY): added clz insns for __ARM_ARCH__ >= 5,
+       (ARM_MOD_BODY): Rewritten. added clz insns for __ARM_ARCH__ >= 5.
+       (ARM_DIV_BODY): Added clz insns for __ARM_ARCH__ >= 5,
        added better divisor alignment in the other case.
-       (ARM_DIV2_ORDER): added, finds the order of a single bit divisor.
+       (ARM_DIV2_ORDER): Added, finds the order of a single bit divisor.
        (__divsi3, __udivsi3, __modsi3, __umodsi3): rewritten using the
        macros above, add fast exits for divisor >= dividend, etc.
 
-2003-09-30  Nicolas Pitre <nico@cam.org>
+2003-09-30  Nicolas Pitre  <nico@cam.org>
 
-       * arm/ieee754-df.S: split compilation of fixunsdfsi from
+       * arm/ieee754-df.S: Split compilation of fixunsdfsi from
        L_fixdfsi target.
-       * arm/t-arm-elf: add _fixunsdfsi target due to the above.
+       * arm/t-arm-elf (LIB1ASMFUNCS): Add _fixunsdfsi.
 
 2003-09-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 

diff --git a/gcc/config/arm/ieee754-sf.S b/gcc/config/arm/ieee754-sf.S
index 904b536..73c598b 100644 (file)
--- a/gcc/config/arm/ieee754-sf.S
+++ b/gcc/config/arm/ieee754-sf.S
@@ -396,7 +396,8 @@ LSYM(Lml_x):
        RET
 
        @ Result is 0, but determine sign anyway.
-LSYM(Lml_z):   eor     r0, r0, r1
+LSYM(Lml_z):
+       eor     r0, r0, r1
        bic     r0, r0, #0x7fffffff
        RET