nand: mtd nand modification

PD#156734: nand: modification
1)sync partition talbe with bootloadr setting.
2)keep compatibale with other platform(a113, etc) when setting lower clock.
3)add a new tested nand flash type

Change-Id: Iff277e6d22bb76c543db76747b22b38f3d60eb11
Signed-off-by: Liang Yang <liang.yang@amlogic.com>

diff --git a/arch/arm64/boot/dts/amlogic/g12a_skt.dts b/arch/arm64/boot/dts/amlogic/g12a_skt.dts
index ca94ebb..2b5381a 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/g12a_skt.dts
+++ b/arch/arm64/boot/dts/amlogic/g12a_skt.dts
@@ -360,11 +360,11 @@
                        };
                        boot{
                                offset=<0x0 0x0>;
-                               size=<0x0 0xF00000>;
+                               size=<0x0 0x1000000>;
                        };
                        system{
                                offset=<0x0 0x0>;
-                               size=<0x0 0x11800000>;
+                               size=<0x0 0x4000000>;
                        };
                        data{
                                offset=<0xffffffff 0xffffffff>;

diff --git a/drivers/amlogic/mtd/m3_nand.c b/drivers/amlogic/mtd/m3_nand.c
index 23f334a..f9c7779 100644 (file)
--- a/drivers/amlogic/mtd/m3_nand.c
+++ b/drivers/amlogic/mtd/m3_nand.c
@@ -309,13 +309,17 @@ static void m3_nand_hw_init(struct aml_nand_chip *aml_chip)
 {
        int sys_clk_rate, bus_cycle, bus_timing;
 
-       sys_clk_rate = 24;
+       if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) {
+               sys_clk_rate = 24;
+               bus_cycle  = 4;
+               bus_timing = 3;
+       } else {
+               sys_clk_rate = 200;
+               bus_cycle  = 6;
+               bus_timing = bus_cycle + 1;
+       }
        get_sys_clk_rate_mtd(controller, &sys_clk_rate);
 
-       /* sys_time = (10000 / sys_clk_rate); */
-       bus_cycle  = 4;
-       bus_timing = 3;
-
        NFC_SET_CFG(controller, 0);
        NFC_SET_TIMING_ASYC(controller, bus_timing, (bus_cycle - 1));
        NFC_SEND_CMD(controller, 1<<31);
@@ -337,14 +341,16 @@ static void m3_nand_adjust_timing(struct aml_nand_chip *aml_chip)
        else
                sys_clk_rate = 250;
 
-       sys_clk_rate = 24;
+       if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) {
+               sys_clk_rate = 24;
+               bus_cycle  = 4;
+               bus_timing = 3;
+       } else {
+               bus_cycle  = 6;
+               bus_timing = bus_cycle + 1;
+       }
        get_sys_clk_rate_mtd(controller, &sys_clk_rate);
 
-       /* sys_time = (10000 / sys_clk_rate); */
-
-       bus_cycle  = 4;
-       bus_timing = 3;
-
        NFC_SET_CFG(controller, 0);
        NFC_SET_TIMING_ASYC(controller, bus_timing, (bus_cycle - 1));
 

diff --git a/drivers/amlogic/mtd/nand_flash.c b/drivers/amlogic/mtd/nand_flash.c
index fa8a037..608d64c 100644 (file)
--- a/drivers/amlogic/mtd/nand_flash.c
+++ b/drivers/amlogic/mtd/nand_flash.c
@@ -425,6 +425,18 @@ struct aml_nand_flash_dev aml_nand_flash_ids[] = {
                0,
                0,
                (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+       {"A revision NAND 2Gib TC58BVG0S3HTA00 ",
+               {NAND_MFR_TOSHIBA, 0xf1, 0x80, 0x15, 0xf2},
+               2048,
+               128,
+               0x20000,
+               64,
+               1,
+               20,
+               25,
+               0,
+               0,
+               (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
        {"A revision NAND 4Gib TH58NVG2S3HTA00 ",
                {NAND_MFR_TOSHIBA, 0xdc, 0x91, 0x15, 0x76},
                2048,