clk: samsung: exynos4: do not define number of clocks in bindings

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 43207257a9cc21f6157c034c92e26f11853a341e..4ec41221e68f4229db3ea08df1c6c101df4d1b45 100644 (file)
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -135,6 +135,9 @@
 #define PWR_CTRL1_USE_CORE1_WFI                        (1 << 1)
 #define PWR_CTRL1_USE_CORE0_WFI                        (1 << 0)
 
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR                                        (CLK_DIV_CORE2 + 1)
+
 /* the exynos4 soc type */
 enum exynos4_soc {
        EXYNOS4210,
@@ -1275,7 +1278,7 @@ static void __init exynos4_clk_init(struct device_node *np,
        if (!reg_base)
                panic("%s: failed to map registers\n", __func__);
 
-       ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
+       ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
        hws = ctx->clk_data.hws;
 
        samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,

diff --git a/drivers/clk/samsung/clk-exynos4412-isp.c b/drivers/clk/samsung/clk-exynos4412-isp.c
index 1470c15e95da3851c7f8e16272a392d81d053660..a70c2b06a61a465e3f8da43dd66b169e7e337d87 100644 (file)
--- a/drivers/clk/samsung/clk-exynos4412-isp.c
+++ b/drivers/clk/samsung/clk-exynos4412-isp.c
@@ -22,6 +22,9 @@
 #define E4X12_GATE_ISP0                0x0800
 #define E4X12_GATE_ISP1                0x0804
 
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_ISP            (CLK_ISP_DIV_MCUISP1 + 1)
+
 /*
  * Support for CMU save/restore across system suspends
  */
@@ -121,7 +124,7 @@ static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev)
        if (!exynos4x12_save_isp)
                return -ENOMEM;
 
-       ctx = samsung_clk_init(dev, reg_base, CLK_NR_ISP_CLKS);
+       ctx = samsung_clk_init(dev, reg_base, CLKS_NR_ISP);
 
        platform_set_drvdata(pdev, ctx);