}
static uint8_t
+count_tes_user_sgprs(const struct radv_pipeline_key *key)
+{
+ unsigned count = 0;
+
+ if (key->dynamic_patch_control_points)
+ count++; /* tes_num_patches */
+
+ return count;
+}
+
+static uint8_t
count_ms_user_sgprs(const struct radv_shader_info *info)
{
uint8_t count = 1 + 3; /* firstTask + num_work_groups[3] */
allocate_user_sgprs(enum amd_gfx_level gfx_level, const struct radv_shader_info *info,
struct radv_shader_args *args, gl_shader_stage stage, bool has_previous_stage,
gl_shader_stage previous_stage, bool needs_view_index, bool has_ngg_query,
+ const struct radv_pipeline_key *key,
struct user_sgpr_info *user_sgpr_info)
{
uint8_t user_sgpr_count = 0;
if (previous_stage == MESA_SHADER_VERTEX)
user_sgpr_count += count_vs_user_sgprs(info);
}
+ if (key->dynamic_patch_control_points)
+ user_sgpr_count += 1; /* tcs_offchip_layout */
break;
case MESA_SHADER_TESS_EVAL:
+ count_tes_user_sgprs(key);
break;
case MESA_SHADER_GEOMETRY:
if (has_previous_stage) {
if (previous_stage == MESA_SHADER_VERTEX) {
user_sgpr_count += count_vs_user_sgprs(info);
+ } else if (previous_stage == MESA_SHADER_TESS_EVAL) {
+ user_sgpr_count += count_tes_user_sgprs(key);
} else if (previous_stage == MESA_SHADER_MESH) {
user_sgpr_count += count_ms_user_sgprs(info);
}
args->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
allocate_user_sgprs(gfx_level, info, args, stage, has_previous_stage, previous_stage,
- needs_view_index, has_ngg_query, &user_sgpr_info);
+ needs_view_index, has_ngg_query, key, &user_sgpr_info);
if (args->explicit_scratch_args) {
ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_CONST_DESC_PTR, &args->ring_offsets);
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.view_index);
}
+ if (key->dynamic_patch_control_points) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->tcs_offchip_layout);
+ }
+
ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tcs_patch_id);
ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tcs_rel_ids);
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.view_index);
}
+ if (key->dynamic_patch_control_points) {
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->tcs_offchip_layout);
+ }
+
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset);
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tcs_factor_offset);
if (args->explicit_scratch_args) {
if (needs_view_index)
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.view_index);
+ if (key->dynamic_patch_control_points)
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->tes_num_patches);
+
if (info->tes.as_es) {
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset);
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.view_index);
}
+ if (previous_stage == MESA_SHADER_TESS_EVAL && key->dynamic_patch_control_points)
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->tes_num_patches);
+
if (info->force_vrs_per_vertex) {
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.force_vrs_rates);
}
case MESA_SHADER_TESS_CTRL:
if (args->ac.view_index.used)
set_loc_shader(args, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
+
+ if (args->tcs_offchip_layout.used)
+ set_loc_shader(args, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
break;
case MESA_SHADER_TESS_EVAL:
if (args->ac.view_index.used)
set_loc_shader(args, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
+
+ if (args->tes_num_patches.used)
+ set_loc_shader(args, AC_UD_TES_NUM_PATCHES, &user_sgpr_idx, 1);
break;
case MESA_SHADER_GEOMETRY:
if (args->ac.view_index.used)
set_loc_shader(args, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
+ if (args->tes_num_patches.used)
+ set_loc_shader(args, AC_UD_TES_NUM_PATCHES, &user_sgpr_idx, 1);
+
if (args->ac.force_vrs_rates.used)
set_loc_shader(args, AC_UD_FORCE_VRS_RATES, &user_sgpr_idx, 1);