Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

+ Add USB host support on VisionFive2 board
+ Enable SPI flash support on VisionFive2 board
+ Enable Random Number Generator in RISC-V QEMU board
+ Display new SBI extension
+ Add SPL_ZERO_MEM_BEFORE_USE Kconfig for jh7110 L2 LIM
  (Loosely-Integrated Memory)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 867cbcb..6771d8d 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -64,6 +64,14 @@ config SPL_SYS_DCACHE_OFF
        help
          Do not enable data cache in SPL.
 
+config SPL_ZERO_MEM_BEFORE_USE
+       bool "Zero memory before use"
+       depends on SPL
+       default n
+       help
+         Zero stack/GD/malloc area in SPL before using them, this is needed for
+         Sifive core devices that uses L2 cache to store SPL.
+
 # board-specific options below
 source "board/AndesTech/ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"

diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 4d95811..8469ee7 100644 (file)
--- a/arch/riscv/cpu/jh7110/Kconfig
+++ b/arch/riscv/cpu/jh7110/Kconfig
@@ -13,6 +13,8 @@ config STARFIVE_JH7110
        select SUPPORT_SPL
        select SPL_RAM if SPL
        select SPL_STARFIVE_DDR
+       select SYS_CACHE_SHIFT_6
+       select SPL_ZERO_MEM_BEFORE_USE
        select PINCTRL_STARFIVE_JH7110
        imply MMC
        imply MMC_BROKEN_CD

diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 72adcef..4047b10 100644 (file)
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -13,7 +13,6 @@
 #include <init.h>
 
 #define CSR_U74_FEATURE_DISABLE        0x7c1
-#define L2_LIM_MEM_END 0x81FFFFFUL
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -59,9 +58,6 @@ int spl_soc_init(void)
 
 void harts_early_init(void)
 {
-       ulong *ptr;
-       u8 *tmp;
-       ulong len, remain;
        /*
         * Feature Disable CSR
         *
@@ -70,25 +66,4 @@ void harts_early_init(void)
         */
        if (CONFIG_IS_ENABLED(RISCV_MMODE))
                csr_write(CSR_U74_FEATURE_DISABLE, 0);
-
-       /* clear L2 LIM  memory
-        * set __bss_end to 0x81FFFFF region to zero
-        * The L2 Cache Controller supports ECC. ECC is applied to SRAM.
-        * If it is not cleared, the ECC part is invalid, and an ECC error
-        * will be reported when reading data.
-        */
-       ptr = (ulong *)&__bss_end;
-       len = L2_LIM_MEM_END - (ulong)&__bss_end;
-       remain = len % sizeof(ulong);
-       len /= sizeof(ulong);
-
-       while (len--)
-               *ptr++ = 0;
-
-       /* clear the remain bytes */
-       if (remain) {
-               tmp = (u8 *)ptr;
-               while (remain--)
-                       *tmp++ = 0;
-       }
 }

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 59d58a5..30cf674 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -111,6 +111,18 @@ call_board_init_f:
  * It's essential before any function call, otherwise, we get data-race.
  */
 
+/* clear stack if necessary */
+#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
+clear_stack:
+       li      t1, 1
+       slli    t1, t1, CONFIG_STACK_SIZE_SHIFT
+       sub     t1, sp, t1
+clear_stack_loop:
+       SREG    zero, 0(t1)             /* t1 is always 16 byte aligned */
+       addi    t1, t1, REGBYTES
+       blt     t1, sp, clear_stack_loop
+#endif
+
 call_board_init_f_0:
        /* find top of reserve space */
 #if CONFIG_IS_ENABLED(SMP)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index bf7fdb4..e40f57a 100644 (file)
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -311,7 +311,7 @@
 
 &pcie0 {
        reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
-       status = "disabled";
+       status = "okay";
 };
 
 &pcie1 {

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 7693699..009a268 100644 (file)
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -31,6 +31,8 @@ enum sbi_ext_id {
        SBI_EXT_DBCN = 0x4442434E,
        SBI_EXT_SUSP = 0x53555350,
        SBI_EXT_CPPC = 0x43505043,
+       SBI_EXT_NACL = 0x4E41434C,
+       SBI_EXT_STA = 0x535441,
 };
 
 enum sbi_ext_base_fid {

diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index b503578..d56b4b5 100644 (file)
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -57,6 +57,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        imply NVME
        imply PCI
        imply PCIE_ECAM_GENERIC
+       imply DM_RNG
        imply SCSI
        imply DM_SCSI
        imply SYS_NS16550

diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index c4707fe..32761c5 100644 (file)
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -27,6 +27,8 @@ static struct sbi_imp implementations[] = {
        { 4, "RustSBI" },
        { 5, "Diosix" },
        { 6, "Coffer" },
+       { 7, "Xen Project" },
+       { 8, "PolarFire Hart Software Services" },
 };
 
 static struct sbi_ext extensions[] = {
@@ -49,6 +51,8 @@ static struct sbi_ext extensions[] = {
        { SBI_EXT_DBCN,                       "Debug Console Extension" },
        { SBI_EXT_SUSP,                       "System Suspend Extension" },
        { SBI_EXT_CPPC,                       "Collaborative Processor Performance Control Extension" },
+       { SBI_EXT_NACL,                       "Nested Acceleration Extension" },
+       { SBI_EXT_STA,                        "Steal-time Accounting Extension" },
 };
 
 static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,

diff --git a/common/init/board_init.c b/common/init/board_init.c
index 96ffb79..ab8c508 100644 (file)
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -162,6 +162,9 @@ void board_init_f_init_reserve(ulong base)
 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
        /* go down one 'early malloc arena' */
        gd->malloc_base = base;
+#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
+       memset((void *)base, '\0', CONFIG_VAL(SYS_MALLOC_F_LEN));
+#endif
 #endif
 
        if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))

diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 5d8a8e2..e9b63e5 100644 (file)
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -6,6 +6,15 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000000
 CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_ENV_SUPPORT=y
+CONFIG_SAVEENV=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE_AUTO=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xf0000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2"
 CONFIG_SPL_TEXT_BASE=0x8000000
@@ -65,6 +74,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_OF_BOARD=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -111,3 +121,7 @@ CONFIG_PINCTRL_STARFIVE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_TIMER_EARLY=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_KEYBOARD=y

diff --git a/drivers/pci/pcie_plda_common.c b/drivers/pci/pcie_plda_common.c
index 005b926..cd74bb4 100644 (file)
--- a/drivers/pci/pcie_plda_common.c
+++ b/drivers/pci/pcie_plda_common.c
@@ -36,8 +36,8 @@ static int plda_pcie_conf_address(const struct udevice *udev, pci_dev_t bdf,
                                  uint offset, void **paddr)
 {
        struct pcie_plda *priv = dev_get_priv(udev);
-       int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf),
-                                    PCI_FUNC(bdf), offset);
+       int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf) - dev_seq(udev),
+                                    PCI_DEV(bdf), PCI_FUNC(bdf), offset);
 
        if (!plda_pcie_addr_valid(priv, bdf))
                return -ENODEV;
@@ -71,6 +71,7 @@ int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
            (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))) {
                priv->sec_busno =
                        ((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value) & 0xff;
+               priv->sec_busno += dev_seq(udev);
                debug("Secondary bus number was changed to %d\n",
                      priv->sec_busno);
        }