drm/amd/display: fix missing writeback disablement if plane is removed

[Why]
If the plane has been removed, the writeback disablement logic
doesn't run

[How]
fix the logic order

Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Roy Chan <roy.chan@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 5c2853654ccad5c891b2cd7144436a7cd5a9e573..a47ba1d45be926a9f761fd9285c07eba270fa66a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1723,13 +1723,15 @@ void dcn20_program_front_end_for_ctx(
 
                                pipe = pipe->bottom_pipe;
                        }
-                       /* Program secondary blending tree and writeback pipes */
-                       pipe = &context->res_ctx.pipe_ctx[i];
-                       if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0
-                                       && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw)
-                                       && hws->funcs.program_all_writeback_pipes_in_tree)
-                               hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
                }
+               /* Program secondary blending tree and writeback pipes */
+               pipe = &context->res_ctx.pipe_ctx[i];
+               if (!pipe->top_pipe && !pipe->prev_odm_pipe
+                               && pipe->stream && pipe->stream->num_wb_info > 0
+                               && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)
+                                       || pipe->stream->update_flags.raw)
+                               && hws->funcs.program_all_writeback_pipes_in_tree)
+                       hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
        }
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 2e8ab9775fa334087305bc70e2c8d5a09eda6b1f..fafed1e4a998d500c3a24712a7c6ea848683b98a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -398,12 +398,22 @@ void dcn30_program_all_writeback_pipes_in_tree(
                        for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {
                                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];
 
+                               if (!pipe_ctx->plane_state)
+                                       continue;
+
                                if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {
                                        wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
                                        break;
                                }
                        }
-                       ASSERT(wb_info.mpcc_inst != -1);
+
+                       if (wb_info.mpcc_inst == -1) {
+                               /* Disable writeback pipe and disconnect from MPCC
+                                * if source plane has been removed
+                                */
+                               dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
+                               continue;
+                       }
 
                        ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
                        dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];