__asm__ __volatile__("wfi" ::: "memory"); \
} while (0)
+/* Get current HART id */
+#define current_hartid() ((unsigned int)csr_read(CSR_MHARTID))
/* determine CPU extension, return non-zero support */
int misa_extension_imp(char ext);
unsigned long next_addr, unsigned long next_mode,
bool next_virt);
-u32 sbi_current_hartid(void);
-
#endif
* Atish Patra <atish.patra@wdc.com>
*/
+#include <sbi/riscv_asm.h>
#include <sbi/sbi_console.h>
#include <sbi/sbi_ecall.h>
#include <sbi/sbi_ecall_interface.h>
{
int ret = 0;
struct sbi_tlb_info tlb_info;
- u32 source_hart = sbi_current_hartid();
+ u32 source_hart = current_hartid();
ulong hmask = 0;
switch (extid) {
* Atish Patra <atish.patra@wdc.com>
*/
+#include <sbi/riscv_asm.h>
#include <sbi/sbi_ecall.h>
#include <sbi/sbi_ecall_interface.h>
#include <sbi/sbi_error.h>
#include <sbi/sbi_ipi.h>
#include <sbi/sbi_timer.h>
#include <sbi/sbi_tlb.h>
-#include <sbi/riscv_asm.h>
static int sbi_ecall_time_handler(struct sbi_scratch *scratch,
unsigned long extid, unsigned long funcid,
{
int ret = 0;
struct sbi_tlb_info tlb_info;
- u32 source_hart = sbi_current_hartid();
+ u32 source_hart = current_hartid();
if (funcid >= SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA &&
funcid <= SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID)
#include <sbi/sbi_hart.h>
#include <sbi/sbi_platform.h>
-/**
- * Return HART ID of the caller.
- */
-unsigned int sbi_current_hartid()
-{
- return (u32)csr_read(CSR_MHARTID);
-}
-
static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
{
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
fail_exit:
/* It should never reach here */
- sbi_printf("ERR: Failed stop hart [%u]\n", sbi_current_hartid());
+ sbi_printf("ERR: Failed stop hart [%u]\n", current_hartid());
sbi_hart_hang();
}
int sbi_hsm_hart_stop(struct sbi_scratch *scratch, bool exitnow)
{
int oldstate;
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
hart_data_offset);
void __noreturn sbi_init(struct sbi_scratch *scratch)
{
bool coldboot = FALSE;
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
if ((SBI_HARTMASK_MAX_BITS <= hartid) ||
*/
void __noreturn sbi_exit(struct sbi_scratch *scratch)
{
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
if (sbi_platform_hart_disabled(plat, hartid))
struct sbi_ipi_data *ipi_data =
sbi_scratch_offset_ptr(scratch, ipi_data_off);
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
sbi_platform_ipi_clear(plat, hartid);
ipi_type = atomic_raw_xchg_ulong(&ipi_data->ipi_type, 0);
* Nick Kossifidis <mick@ics.forth.gr>
*/
+#include <sbi/riscv_asm.h>
#include <sbi/sbi_bitops.h>
#include <sbi/sbi_hart.h>
#include <sbi/sbi_hsm.h>
void __noreturn sbi_system_reboot(struct sbi_scratch *scratch, u32 type)
{
ulong hbase = 0, hmask;
- u32 current_hartid = sbi_current_hartid();
+ u32 cur_hartid = current_hartid();
/* Send HALT IPI to every hart other than the current hart */
while (!sbi_hsm_hart_started_mask(scratch, hbase, &hmask)) {
- if (hbase <= current_hartid)
- hmask &= ~(1UL << (current_hartid - hbase));
+ if (hbase <= cur_hartid)
+ hmask &= ~(1UL << (cur_hartid - hbase));
if (hmask)
sbi_ipi_send_halt(scratch, hmask, hbase);
hbase += BITS_PER_LONG;
void __noreturn sbi_system_shutdown(struct sbi_scratch *scratch, u32 type)
{
ulong hbase = 0, hmask;
- u32 current_hartid = sbi_current_hartid();
+ u32 cur_hartid = current_hartid();
/* Send HALT IPI to every hart other than the current hart */
while (!sbi_hsm_hart_started_mask(scratch, hbase, &hmask)) {
- if (hbase <= current_hartid)
- hmask &= ~(1UL << (current_hartid - hbase));
+ if (hbase <= cur_hartid)
+ hmask &= ~(1UL << (cur_hartid - hbase));
if (hmask)
sbi_ipi_send_halt(scratch, hmask, hbase);
hbase += BITS_PER_LONG;
int ret;
struct sbi_fifo *tlb_fifo_r;
struct sbi_tlb_info *tinfo = data;
- u32 curr_hartid = sbi_current_hartid();
+ u32 curr_hartid = current_hartid();
/*
* If address range to flush is too big then simply
{
int rc = SBI_ENOTSUPP;
const char *msg = "trap handler failed";
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
ulong mcause = csr_read(CSR_MCAUSE);
ulong mtval = csr_read(CSR_MTVAL), mtval2 = 0, mtinst = 0;
struct sbi_trap_info trap, *uptrap;
* Anup Patel <anup.patel@wdc.com>
*/
-#include <sbi/riscv_io.h>
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_atomic.h>
-#include <sbi/sbi_hart.h>
+#include <sbi/riscv_io.h>
#include <sbi_utils/sys/clint.h>
static u32 clint_ipi_hart_count;
int clint_warm_ipi_init(void)
{
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
if (!clint_ipi_base)
return -1;
void clint_timer_event_stop(void)
{
- u32 target_hart = sbi_current_hartid();
+ u32 target_hart = current_hartid();
if (clint_time_hart_count <= target_hart)
return;
void clint_timer_event_start(u64 next_event)
{
- u32 target_hart = sbi_current_hartid();
+ u32 target_hart = current_hartid();
if (clint_time_hart_count <= target_hart)
return;
int clint_warm_timer_init(void)
{
- u32 target_hart = sbi_current_hartid();
+ u32 target_hart = current_hartid();
if (clint_time_hart_count <= target_hart || !clint_time_base)
return -1;
* Nylon Chen <nylon7@andestech.com>
*/
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/sbi_const.h>
-#include <sbi/sbi_hart.h>
#include <sbi/sbi_platform.h>
#include <sbi/sbi_console.h>
#include <sbi_utils/serial/uart8250.h>
/* Initialize the platform interrupt controller for current HART. */
static int ae350_irqchip_init(bool cold_boot)
{
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
int ret;
if (cold_boot) {
* Nylon Chen <nylon7@andestech.com>
*/
-#include <sbi/sbi_types.h>
-#include <sbi/sbi_hart.h>
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_io.h>
+#include <sbi/sbi_types.h>
#include "plicsw.h"
#include "platform.h"
static inline void plicsw_claim(void)
{
- u32 source_hart = sbi_current_hartid();
+ u32 source_hart = current_hartid();
plicsw_dev[source_hart].source_id =
readl(plicsw_dev[source_hart].plicsw_claim);
static inline void plicsw_complete(void)
{
- u32 source_hart = sbi_current_hartid();
+ u32 source_hart = current_hartid();
u32 source = plicsw_dev[source_hart].source_id;
writel(source, plicsw_dev[source_hart].plicsw_claim);
* The bit 5 is used to send IPI to hart 2
* The bit 4 is used to send IPI to hart 3
*/
- u32 source_hart = sbi_current_hartid();
+ u32 source_hart = current_hartid();
u32 target_offset = (PLICSW_PENDING_PER_HART - 1) - target_hart;
u32 per_hart_offset = PLICSW_PENDING_PER_HART * source_hart;
u32 val = 1 << target_offset << per_hart_offset;
int plicsw_warm_ipi_init(void)
{
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
if (!plicsw_dev[hartid].plicsw_pending
&& !plicsw_dev[hartid].plicsw_enable
* Nylon Chen <nylon7@andestech.com>
*/
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_io.h>
-#include <sbi/sbi_hart.h>
static u32 plmt_time_hart_count;
static volatile void *plmt_time_base;
void plmt_timer_event_stop(void)
{
- u32 target_hart = sbi_current_hartid();
+ u32 target_hart = current_hartid();
if (plmt_time_hart_count <= target_hart)
return;
void plmt_timer_event_start(u64 next_event)
{
- u32 target_hart = sbi_current_hartid();
+ u32 target_hart = current_hartid();
if (plmt_time_hart_count <= target_hart)
return;
int plmt_warm_timer_init(void)
{
- u32 target_hart = sbi_current_hartid();
+ u32 target_hart = current_hartid();
if (plmt_time_hart_count <= target_hart || !plmt_time_base)
return -1;
* Panagiotis Peristerakis <perister@ics.forth.gr>
*/
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/sbi_const.h>
#include <sbi/sbi_platform.h>
*/
static int ariane_irqchip_init(bool cold_boot)
{
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
int ret;
if (cold_boot) {
* Damien Le Moal <damien.lemoal@wdc.com>
*/
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/sbi_const.h>
-#include <sbi/sbi_hart.h>
#include <sbi/sbi_platform.h>
#include <sbi/sbi_console.h>
#include <sbi_utils/irqchip/plic.h>
static int k210_irqchip_init(bool cold_boot)
{
int rc;
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
if (cold_boot) {
rc = plic_cold_irqchip_init(K210_PLIC_BASE_ADDR,
* Nick Kossifidis <mick@ics.forth.gr>
*/
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/riscv_io.h>
#include <sbi/sbi_const.h>
static int virt_irqchip_init(bool cold_boot)
{
int rc;
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
if (cold_boot) {
rc = plic_cold_irqchip_init(
#include <libfdt.h>
#include <fdt.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_io.h>
#include <sbi/riscv_encoding.h>
#include <sbi/sbi_const.h>
-#include <sbi/sbi_hart.h>
#include <sbi/sbi_console.h>
#include <sbi/sbi_platform.h>
-#include <sbi/riscv_io.h>
#include <sbi_utils/irqchip/plic.h>
#include <sbi_utils/serial/sifive-uart.h>
#include <sbi_utils/sys/clint.h>
static int fu540_irqchip_init(bool cold_boot)
{
int rc;
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
if (cold_boot) {
rc = plic_cold_irqchip_init(FU540_PLIC_ADDR,
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
*/
+#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/sbi_const.h>
#include <sbi/sbi_platform.h>
*/
static int platform_irqchip_init(bool cold_boot)
{
- u32 hartid = sbi_current_hartid();
+ u32 hartid = current_hartid();
int ret;
/* Example if the generic PLIC driver is used */