[LiveIntervals] Fix repairOldRegInRange for simple def cases

The fix applied in D23303 "LiveIntervalAnalysis: fix a crash in repairOldRegInRange"
was over-zealous. It would bail out when the end of the range to be
repaired was in the middle of the first segment of the live range of
Reg, which was always the case when the range contained a single def of
Reg.

This patch fixes it as suggested by Matthias Braun in post-commit review
on the original patch, and tests it by adding -early-live-intervals to
a selection of existing lit tests that now pass.

(Note that D23303 was originally applied to fix a crash in
SILoadStoreOptimizer, but that is now moot since D23814 updated
SILoadStoreOptimizer to run before scheduling so it no longer has to
update live intervals.)

Differential Revision: https://reviews.llvm.org/D110238

diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
index 23036c2..ac6818a 100644 (file)
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -1571,15 +1571,14 @@ void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
                                         LaneBitmask LaneMask) {
   LiveInterval::iterator LII = LR.find(EndIdx);
   SlotIndex lastUseIdx;
-  if (LII == LR.begin()) {
-    // This happens when the function is called for a subregister that only
-    // occurs _after_ the range that is to be repaired.
-    return;
-  }
-  if (LII != LR.end() && LII->start < EndIdx)
+  if (LII != LR.end() && LII->start < EndIdx) {
     lastUseIdx = LII->end;
-  else
+  } else if (LII == LR.begin()) {
+    // We may not have a liverange at all if this is a subregister untouched
+    // between \p Begin and \p End.
+  } else {
     --LII;
+  }
 
   for (MachineBasicBlock::iterator I = End; I != Begin;) {
     --I;

diff --git a/llvm/test/CodeGen/AMDGPU/extract-load-i1.ll b/llvm/test/CodeGen/AMDGPU/extract-load-i1.ll
index 5a4c83d..042de0c 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/extract-load-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-load-i1.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -early-live-intervals < %s | FileCheck %s
 
 ; FIXME: Inefficient codegen which skips an optimization of load +
 ; extractelement when the vector element type is not byte-sized.

diff --git a/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
new file mode 100644 (file)
index 0000000..72cd2ee
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=liveintervals,twoaddressinstruction,simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s
+
+# Check that LiveIntervals are correctly updated when eliminating REG_SEQUENCE.
+---
+name: f
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: f
+    ; CHECK: liveins: $vgpr0, $vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: undef %2.sub0:vreg_64 = COPY $vgpr0
+    ; CHECK-NEXT: %2.sub1:vreg_64 = COPY $vgpr1
+    ; CHECK-NEXT: $vgpr2_vgpr3 = COPY %2
+    ; CHECK-NEXT: S_NOP 0, implicit $vgpr2_vgpr3
+    %0:vgpr_32 = COPY $vgpr0
+    %1:vgpr_32 = COPY $vgpr1
+    %35:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
+    $vgpr2_vgpr3 = COPY %35
+    S_NOP 0, implicit $vgpr2_vgpr3
+...

diff --git a/llvm/test/CodeGen/ARM/signext-inreg.ll b/llvm/test/CodeGen/ARM/signext-inreg.ll
index dd8b144..e41af81 100644 (file)
--- a/llvm/test/CodeGen/ARM/signext-inreg.ll
+++ b/llvm/test/CodeGen/ARM/signext-inreg.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=armv8 | FileCheck %s
+; RUN: llc < %s -mtriple=armv8 -early-live-intervals | FileCheck %s
 define <4 x i32> @test(<4 x i32> %m) {
 ; CHECK-LABEL: test:
 ; CHECK:       @ %bb.0: @ %entry

diff --git a/llvm/test/CodeGen/X86/mul-shift-reassoc.ll b/llvm/test/CodeGen/X86/mul-shift-reassoc.ll
index 74ae976..53d7a78 100644 (file)
--- a/llvm/test/CodeGen/X86/mul-shift-reassoc.ll
+++ b/llvm/test/CodeGen/X86/mul-shift-reassoc.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
+; RUN: llc < %s -mtriple=i686-- -early-live-intervals | FileCheck %s
 
 define i32 @test(i32 %X, i32 %Y) {
        ; Push the shl through the mul to allow an LEA to be formed, instead