Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
{
if (b == 0) {
env->sregs[SR_MSR] |= MSR_DZ;
- /* FIXME: Raise the div by zero exception. */
+
+ if ((env->sregs[SR_MSR] & MSR_EE)
+ && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
+ env->sregs[SR_ESR] = ESR_EC_DIVZERO;
+ helper_raise_exception(EXCP_HW_EXCP);
+ }
return 0;
}
env->sregs[SR_MSR] &= ~MSR_DZ;
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
- /* FIXME: support div by zero exceptions. */
if (u)
gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
else