* r5900.igen (CVT.W.S): Always round towards zero.

Update testsuite.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 4176bd5..67393ed 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,9 @@
+start-sanitize-r5900
+Mon Nov 16 11:44:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * r5900.igen (CVT.W.S): Always round towards zero.
+
+end-sanitize-r5900
 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 
        * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK