lavapipe: accurately set image/ssbo access based on shader usage

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15233>

diff --git a/src/gallium/frontends/lavapipe/lvp_execute.c b/src/gallium/frontends/lavapipe/lvp_execute.c
index 815f1eb..271a0a9 100644 (file)
--- a/src/gallium/frontends/lavapipe/lvp_execute.c
+++ b/src/gallium/frontends/lavapipe/lvp_execute.c
@@ -42,6 +42,7 @@
 #include "util/u_prim_restart.h"
 #include "util/format/u_format_zs.h"
 #include "util/ptralloc.h"
+#include "tgsi/tgsi_from_mesa.h"
 
 #include "vk_util.h"
 
@@ -116,6 +117,8 @@ struct rendering_state {
    struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
    struct cso_velems_state velem;
 
+   struct lvp_access_info access[MESA_SHADER_STAGES];
+
    struct pipe_sampler_view *sv[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
    int num_sampler_views[PIPE_SHADER_TYPES];
    struct pipe_sampler_state ss[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];
@@ -335,7 +338,7 @@ static void emit_state(struct rendering_state *state)
       if (state->sb_dirty[sh]) {
          state->pctx->set_shader_buffers(state->pctx, sh,
                                          0, state->num_shader_buffers[sh],
-                                         state->sb[sh], (1 << state->num_shader_buffers[sh]) - 1);
+                                         state->sb[sh], state->access[tgsi_processor_to_shader_stage(sh)].buffers_written);
       }
    }
 
@@ -380,6 +383,8 @@ static void handle_compute_pipeline(struct vk_cmd_queue_entry *cmd,
 {
    LVP_FROM_HANDLE(lvp_pipeline, pipeline, cmd->u.bind_pipeline.pipeline);
 
+   memcpy(&state->access[MESA_SHADER_COMPUTE], &pipeline->access[MESA_SHADER_COMPUTE], sizeof(struct lvp_access_info));
+
    state->dispatch_info.block[0] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[0];
    state->dispatch_info.block[1] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[1];
    state->dispatch_info.block[2] = pipeline->pipeline_nir[MESA_SHADER_COMPUTE]->info.workgroup_size[2];
@@ -489,6 +494,8 @@ static void handle_graphics_pipeline(struct vk_cmd_queue_entry *cmd,
    unsigned fb_samples = 0;
    bool clip_halfz = state->rs_state.clip_halfz;
 
+   memcpy(state->access, pipeline->access, sizeof(struct lvp_access_info) * 5); //4 vertex stages + fragment
+
    memset(dynamic_states, 0, sizeof(dynamic_states));
    if (pipeline->graphics_create_info.pDynamicState)
    {
@@ -1136,8 +1143,19 @@ static void fill_image_view_stage(struct rendering_state *state,
       state->iv[p_stage][idx].u.tex.last_layer = iv->subresourceRange.baseArrayLayer + lvp_get_layerCount(iv->image, &iv->subresourceRange) - 1;
    }
    state->iv[p_stage][idx].u.tex.level = iv->subresourceRange.baseMipLevel;
-   state->iv[p_stage][idx].access = PIPE_IMAGE_ACCESS_READ_WRITE;
-   state->iv[p_stage][idx].shader_access = PIPE_IMAGE_ACCESS_READ_WRITE;
+
+   assert(idx < 32);
+   state->iv[p_stage][idx].access = 0;
+   state->iv[p_stage][idx].shader_access = 0;
+   if (state->access[stage].images_read & BITFIELD_BIT(idx)) {
+      state->iv[p_stage][idx].access |= PIPE_IMAGE_ACCESS_READ;
+      state->iv[p_stage][idx].shader_access |= PIPE_IMAGE_ACCESS_READ;
+   }
+   if (state->access[stage].images_written & BITFIELD_BIT(idx)) {
+      state->iv[p_stage][idx].access |= PIPE_IMAGE_ACCESS_WRITE;
+      state->iv[p_stage][idx].shader_access |= PIPE_IMAGE_ACCESS_WRITE;
+   }
+
    if (state->num_shader_images[p_stage] <= idx)
       state->num_shader_images[p_stage] = idx + 1;