;; In 64 bit mode, 32 bit values in general registers are always
;; correctly sign extended. That means that if the target is a
;; general register, we can sign extend from SImode to DImode just by
-;; doing a move.
+;; doing a move. The matching define_insns are *movdi_internal2_extend
+;; and *movdi_internal2_mips16.
-(define_insn "extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "=d,y,d,*d,d,d")
- (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,d,y,*x,R,m")))]
+(define_expand "extendsidi2"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
"TARGET_64BIT"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,move,move,hilo,load,load")
- (set_attr "mode" "DI")
- (set_attr "length" "4,4,4,4,4,8")])
+ "")
;; These patterns originally accepted general_operands, however, slightly
;; better code is generated by only accepting register_operands, and then
;;
;; ....................
-;; The SImode scratch register can not be shared with address regs used for
-;; operand zero, because then the address in the move instruction will be
-;; clobbered. We mark the scratch register as early clobbered to prevent this.
-
-;; We need the ?X in alternative 1 so that it will be chosen only if the
-;; destination is a floating point register. Otherwise, alternative 1 can
-;; have lower cost than alternative 0 (because there is one less loser), and
-;; can be chosen when it won't work (because integral reloads into FP
-;; registers are not supported).
-
-(define_insn "fix_truncdfsi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,*f,R,To")
- (fix:SI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
- (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
- (clobber (match_scratch:DF 3 "=f,?*X,f,f"))]
+(define_expand "fix_truncdfsi2"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (fix:SI (match_operand:DF 1 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
{
- rtx xoperands[10];
-
- if (which_alternative == 1)
- return \"trunc.w.d %0,%1,%2\";
-
- output_asm_insn (\"trunc.w.d %3,%1,%2\", operands);
+ if (!ISA_HAS_TRUNC_W)
+ {
+ emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
+ DONE;
+ }
+})
- xoperands[0] = operands[0];
- xoperands[1] = operands[3];
- output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
- return \"\";
-}"
+(define_insn "fix_truncdfsi2_insn"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (fix:SI (match_operand:DF 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
+ "trunc.w.d %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
- (set_attr "length" "44,36,40,44")])
-
+ (set_attr "length" "4")])
+
+(define_insn "fix_truncdfsi2_macro"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (fix:SI (match_operand:DF 1 "register_operand" "f")))
+ (clobber (match_scratch:DF 2 "=d"))]
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
+ "trunc.w.d %0,%1,%2"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "DF")
+ (set_attr "length" "36")])
-(define_insn "fix_truncsfsi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,*f,R,To")
- (fix:SI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
- (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
- (clobber (match_scratch:SF 3 "=f,?*X,f,f"))]
+(define_expand "fix_truncsfsi2"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (fix:SI (match_operand:SF 1 "register_operand" "f")))]
"TARGET_HARD_FLOAT"
- "*
{
- rtx xoperands[10];
-
- if (which_alternative == 1)
- return \"trunc.w.s %0,%1,%2\";
-
- output_asm_insn (\"trunc.w.s %3,%1,%2\", operands);
+ if (!ISA_HAS_TRUNC_W)
+ {
+ emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
+ DONE;
+ }
+})
- xoperands[0] = operands[0];
- xoperands[1] = operands[3];
- output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
- return \"\";
-}"
+(define_insn "fix_truncsfsi2_insn"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (fix:SI (match_operand:SF 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
+ "trunc.w.s %0,%1"
[(set_attr "type" "fcvt")
- (set_attr "mode" "SF")
- (set_attr "length" "44,36,40,44")])
-
+ (set_attr "mode" "DF")
+ (set_attr "length" "4")])
+
+(define_insn "fix_truncsfsi2_macro"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (fix:SI (match_operand:SF 1 "register_operand" "f")))
+ (clobber (match_scratch:SF 2 "=d"))]
+ "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
+ "trunc.w.s %0,%1,%2"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "DF")
+ (set_attr "length" "36")])
;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals
;;; but not in the chapter that describes the FPU. It is not mentioned at all
;;; If this is disabled, then fixuns_truncdfdi2 must be disabled also.
(define_insn "fix_truncdfdi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,*f,R,To")
- (fix:DI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
- (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "*
-{
- rtx xoperands[10];
-
- if (which_alternative == 1)
- return \"trunc.l.d %0,%1\";
-
- output_asm_insn (\"trunc.l.d %2,%1\", operands);
-
- xoperands[0] = operands[0];
- xoperands[1] = operands[2];
- output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
- return \"\";
-}"
+ [(set (match_operand:DI 0 "register_operand" "=f")
+ (fix:DI (match_operand:DF 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
+ "trunc.l.d %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
- (set_attr "length" "8,4,8,12")])
+ (set_attr "length" "4")])
;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals
;;; but not in the chapter that describes the FPU. It is not mentioned at all
;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
(define_insn "fix_truncsfdi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,*f,R,To")
- (fix:DI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
- (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "*
-{
- rtx xoperands[10];
-
- if (which_alternative == 1)
- return \"trunc.l.s %0,%1\";
-
- output_asm_insn (\"trunc.l.s %2,%1\", operands);
-
- xoperands[0] = operands[0];
- xoperands[1] = operands[2];
- output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
- return \"\";
-}"
+ [(set (match_operand:DI 0 "register_operand" "=f")
+ (fix:DI (match_operand:SF 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
+ "trunc.l.s %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
- (set_attr "length" "8,4,8,12")])
+ (set_attr "length" "4")])
(define_insn "floatsidf2"
- [(set (match_operand:DF 0 "register_operand" "=f,f,f")
- (float:DF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (float:DF (match_operand:SI 1 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "*
-{
- dslots_load_total++;
- if (GET_CODE (operands[1]) == MEM)
- return \"l.s\\t%0,%1%#\;cvt.d.w\\t%0,%0\";
-
- return \"mtc1\\t%1,%0%#\;cvt.d.w\\t%0,%0\";
-}"
+ "cvt.d.w\\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
- (set_attr "length" "12,16,12")])
+ (set_attr "length" "4")])
(define_insn "floatdidf2"
- [(set (match_operand:DF 0 "register_operand" "=f,f,f")
- (float:DF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "*
-{
- dslots_load_total++;
- if (GET_CODE (operands[1]) == MEM)
- return \"l.d\\t%0,%1%#\;cvt.d.l\\t%0,%0\";
-
- return \"dmtc1\\t%1,%0%#\;cvt.d.l\\t%0,%0\";
-}"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (float:DF (match_operand:DI 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
+ "cvt.d.l\\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
- (set_attr "length" "12,16,12")])
+ (set_attr "length" "4")])
(define_insn "floatsisf2"
- [(set (match_operand:SF 0 "register_operand" "=f,f,f")
- (float:SF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (float:SF (match_operand:SI 1 "register_operand" "f")))]
"TARGET_HARD_FLOAT"
- "*
-{
- dslots_load_total++;
- if (GET_CODE (operands[1]) == MEM)
- return \"l.s\\t%0,%1%#\;cvt.s.w\\t%0,%0\";
-
- return \"mtc1\\t%1,%0%#\;cvt.s.w\\t%0,%0\";
-}"
+ "cvt.s.w\\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
- (set_attr "length" "12,16,12")])
+ (set_attr "length" "4")])
(define_insn "floatdisf2"
- [(set (match_operand:SF 0 "register_operand" "=f,f,f")
- (float:SF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
- "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
- "*
-{
- dslots_load_total++;
- if (GET_CODE (operands[1]) == MEM)
- return \"l.d\\t%0,%1%#\;cvt.s.l\\t%0,%0\";
-
- return \"dmtc1\\t%1,%0%#\;cvt.s.l\\t%0,%0\";
-}"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (float:SF (match_operand:DI 1 "register_operand" "f")))]
+ "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
+ "cvt.s.l\\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
- (set_attr "length" "12,16,12")])
+ (set_attr "length" "4")])
(define_expand "fixuns_truncdfsi2"
"")
(define_insn "movdi_internal2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m,*x,*d,*x,*a,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R")
- (match_operand:DI 1 "movdi_operand" "d,IKL,Mnis,R,m,dJ,dJ,J,*x,*d,*J,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m,*f,*f,*f,*f,*d,*R,*m,*x,*d,*x,*a,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R")
+ (match_operand:DI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ,*f,*d*J,*R,*m,*f,*f,*f,*J,*x,*d,*J,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D"))]
"TARGET_64BIT && !TARGET_MIPS16
&& (register_operand (operands[0], DImode)
- || se_register_operand (operands[1], DImode)
+ || register_operand (operands[1], DImode)
|| (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
|| operands[1] == CONST0_RTX (DImode))"
"* return mips_move_2words (operands, insn); "
- [(set_attr "type" "move,arith,arith,load,load,store,store,hilo,hilo,hilo,hilo,xfer,load,load,xfer,store,store")
+ [(set_attr "type" "move,arith,arith,load,load,store,store,move,xfer,load,load,xfer,store,store,hilo,hilo,hilo,hilo,xfer,load,load,xfer,store,store")
(set_attr "mode" "DI")
- (set_attr "length" "4,4,8,4,8,4,8,4,4,4,8,8,8,8,8,8,8")])
+ (set_attr "length" "4,4,8,4,8,4,8,4,4,4,8,4,4,8,4,4,4,8,8,8,8,8,8,8")])
-(define_insn ""
+;; Sign-extended operands are reloaded using this instruction, so the
+;; constraints must handle every SImode source operand X and destination
+;; register R for which:
+;;
+;; mips_secondary_reload_class (CLASS_OF (R), DImode, true,
+;; gen_rtx_SIGN_EXTEND (DImode, X))
+;;
+;; returns NO_REGS. Also handle memory destinations, where allowed.
+;;
+;; This pattern is essentially a trimmed-down version of movdi_internal2.
+;; The main difference is that dJ -> f and f -> d are the only constraints
+;; involving float registers. See mips_secondary_reload_class for details.
+(define_insn "*movdi_internal2_extend"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m,*d,*f,*x,*d,*x,*a,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R")
+ (sign_extend:DI (match_operand:SI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ,*f,*d*J,*J,*x,*d,*J,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D")))]
+ "TARGET_64BIT && !TARGET_MIPS16
+ && (register_operand (operands[0], DImode)
+ || register_operand (operands[1], DImode)
+ || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
+ || operands[1] == CONST0_RTX (DImode))"
+ "* return mips_sign_extend (insn, operands[0], operands[1]);"
+ [(set_attr "type" "move,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo,hilo,hilo,xfer,load,load,xfer,store,store")
+ (set_attr "mode" "DI")
+ (set_attr "length" "4,4,8,4,8,4,8,4,4,4,4,4,8,8,8,8,8,8,8")])
+
+(define_insn "*movdi_internal2_mips16"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,R,m,*d")
(match_operand:DI 1 "movdi_operand" "d,d,y,K,N,s,R,m,d,d,*x"))]
"TARGET_64BIT && TARGET_MIPS16
;; The difference between these two is whether or not ints are allowed
;; in FP registers (off by default, use -mdebugh to enable).
-(define_insn "movsi_internal1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x,*x,*d,*d,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R")
- (match_operand:SI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,J,*d,*x,*a,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D"))]
- "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo,hilo,hilo,xfer,load,load,xfer,store,store")
- (set_attr "mode" "SI")
- (set_attr "length" "4,4,8,4,8,4,8,4,4,4,4,8,4,8,4,4,4,4,4,4,8,4,4,8")])
-
-(define_insn "movsi_internal2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R")
- (match_operand:SI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x,*d,*a,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D"))]
- "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
+(define_insn "movsi_internal"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m,*f,*f,*f,?*f,*d,*R,*m,*d,*z,*x,*d,*x,*d,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R")
+ (match_operand:SI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ,*f,*d*J,*R,*m,*f,*f,*f,*z,*d,J,*x,*d,*a,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D"))]
+ "!TARGET_MIPS16
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode)
|| (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
"* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "move,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo,hilo,hilo,xfer,load,load,xfer,store,store")
+ [(set_attr "type" "move,arith,arith,load,load,store,store,move,xfer,load,load,xfer,store,store,xfer,xfer,hilo,hilo,hilo,hilo,xfer,load,load,xfer,store,store")
(set_attr "mode" "SI")
- (set_attr "length" "4,4,8,4,8,4,8,4,4,4,4,4,4,4,4,8,4,4,8")])
+ (set_attr "length" "4,4,8,4,8,4,8,4,4,4,8,4,4,8,4,4,4,4,4,4,4,4,8,4,4,8")])
;; This is the mips16 movsi instruction. We accept a small integer as
;; the source if the destination is a GP memory reference. This is
;; The difference between these two is whether or not ints are allowed
;; in FP registers (off by default, use -mdebugh to enable).
-(define_insn "movhi_internal1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x,*d")
+(define_insn "movhi_internal"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d")
(match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
- "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
+ "!TARGET_MIPS16
&& (register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode)
|| (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
(set_attr "mode" "HI")
(set_attr "length" "4,4,4,8,4,8,4,4,4,4,4")])
-(define_insn "movhi_internal2"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
- (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
- "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], HImode)
- || register_operand (operands[1], HImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
- (set_attr "mode" "HI")
- (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
-
(define_insn ""
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
(match_operand:HI 1 "general_operand" "d,d,y,K,N,R,m,d,d,*x"))]
;; The difference between these two is whether or not ints are allowed
;; in FP registers (off by default, use -mdebugh to enable).
-(define_insn "movqi_internal1"
+(define_insn "movqi_internal"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d")
(match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
- "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
+ "!TARGET_MIPS16
&& (register_operand (operands[0], QImode)
|| register_operand (operands[1], QImode)
|| (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
(set_attr "mode" "QI")
(set_attr "length" "4,4,4,8,4,8,4,4,4,4,4")])
-(define_insn "movqi_internal2"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
- (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
- "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
- && (register_operand (operands[0], QImode)
- || register_operand (operands[1], QImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
- "* return mips_move_1word (operands, insn, TRUE);"
- [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
- (set_attr "mode" "QI")
- (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
-
(define_insn ""
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
(match_operand:QI 1 "general_operand" "d,d,y,K,N,R,m,d,d,*x"))]