clk: sunxi: Implement SPI clocks, resets

- Implement SPI AHB, MOD clocks via ccu_clk_gate for all
  supported Allwinner SoCs
- Implement SPI resets via ccu_reset for all supported
  Allwinner SoCs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index 2aa41ef..b8b57e2 100644 (file)
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -22,6 +22,10 @@ static struct ccu_clk_gate a10_gates[] = {
        [CLK_AHB_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_AHB_MMC2]          = GATE(0x060, BIT(10)),
        [CLK_AHB_MMC3]          = GATE(0x060, BIT(11)),
+       [CLK_AHB_SPI0]          = GATE(0x060, BIT(20)),
+       [CLK_AHB_SPI1]          = GATE(0x060, BIT(21)),
+       [CLK_AHB_SPI2]          = GATE(0x060, BIT(22)),
+       [CLK_AHB_SPI3]          = GATE(0x060, BIT(23)),
 
        [CLK_APB1_UART0]        = GATE(0x06c, BIT(16)),
        [CLK_APB1_UART1]        = GATE(0x06c, BIT(17)),
@@ -32,9 +36,15 @@ static struct ccu_clk_gate a10_gates[] = {
        [CLK_APB1_UART6]        = GATE(0x06c, BIT(22)),
        [CLK_APB1_UART7]        = GATE(0x06c, BIT(23)),
 
+       [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
+       [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
+       [CLK_SPI2]              = GATE(0x0a8, BIT(31)),
+
        [CLK_USB_OHCI0]         = GATE(0x0cc, BIT(6)),
        [CLK_USB_OHCI1]         = GATE(0x0cc, BIT(7)),
        [CLK_USB_PHY]           = GATE(0x0cc, BIT(8)),
+
+       [CLK_SPI3]              = GATE(0x0d4, BIT(31)),
 };
 
 static struct ccu_reset a10_resets[] = {

diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index 87b74e5..c6fcede 100644 (file)
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -19,12 +19,19 @@ static struct ccu_clk_gate a10s_gates[] = {
        [CLK_AHB_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_AHB_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_AHB_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_AHB_SPI0]          = GATE(0x060, BIT(20)),
+       [CLK_AHB_SPI1]          = GATE(0x060, BIT(21)),
+       [CLK_AHB_SPI2]          = GATE(0x060, BIT(22)),
 
        [CLK_APB1_UART0]        = GATE(0x06c, BIT(16)),
        [CLK_APB1_UART1]        = GATE(0x06c, BIT(17)),
        [CLK_APB1_UART2]        = GATE(0x06c, BIT(18)),
        [CLK_APB1_UART3]        = GATE(0x06c, BIT(19)),
 
+       [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
+       [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
+       [CLK_SPI2]              = GATE(0x0a8, BIT(31)),
+
        [CLK_USB_OHCI]          = GATE(0x0cc, BIT(6)),
        [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
        [CLK_USB_PHY1]          = GATE(0x0cc, BIT(9)),

diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index 1ef2359..c160192 100644 (file)
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -16,6 +16,8 @@ static struct ccu_clk_gate a23_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
+       [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_BUS_OTG]           = GATE(0x060, BIT(24)),
        [CLK_BUS_EHCI]          = GATE(0x060, BIT(26)),
        [CLK_BUS_OHCI]          = GATE(0x060, BIT(29)),
@@ -26,6 +28,9 @@ static struct ccu_clk_gate a23_gates[] = {
        [CLK_BUS_UART3]         = GATE(0x06c, BIT(19)),
        [CLK_BUS_UART4]         = GATE(0x06c, BIT(20)),
 
+       [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
+       [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
+
        [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
        [CLK_USB_PHY1]          = GATE(0x0cc, BIT(9)),
        [CLK_USB_HSIC]          = GATE(0x0cc, BIT(10)),
@@ -41,6 +46,8 @@ static struct ccu_reset a23_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
+       [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(24)),
        [RST_BUS_EHCI]          = RESET(0x2c0, BIT(26)),
        [RST_BUS_OHCI]          = RESET(0x2c0, BIT(29)),

diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 5bd8b7d..fa6e3ee 100644 (file)
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -17,6 +17,10 @@ static struct ccu_clk_gate a31_gates[] = {
        [CLK_AHB1_MMC1]         = GATE(0x060, BIT(9)),
        [CLK_AHB1_MMC2]         = GATE(0x060, BIT(10)),
        [CLK_AHB1_MMC3]         = GATE(0x060, BIT(11)),
+       [CLK_AHB1_SPI0]         = GATE(0x060, BIT(20)),
+       [CLK_AHB1_SPI1]         = GATE(0x060, BIT(21)),
+       [CLK_AHB1_SPI2]         = GATE(0x060, BIT(22)),
+       [CLK_AHB1_SPI3]         = GATE(0x060, BIT(23)),
        [CLK_AHB1_OTG]          = GATE(0x060, BIT(24)),
        [CLK_AHB1_EHCI0]        = GATE(0x060, BIT(26)),
        [CLK_AHB1_EHCI1]        = GATE(0x060, BIT(27)),
@@ -31,6 +35,11 @@ static struct ccu_clk_gate a31_gates[] = {
        [CLK_APB2_UART4]        = GATE(0x06c, BIT(20)),
        [CLK_APB2_UART5]        = GATE(0x06c, BIT(21)),
 
+       [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
+       [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
+       [CLK_SPI2]              = GATE(0x0a8, BIT(31)),
+       [CLK_SPI3]              = GATE(0x0ac, BIT(31)),
+
        [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
        [CLK_USB_PHY1]          = GATE(0x0cc, BIT(9)),
        [CLK_USB_PHY2]          = GATE(0x0cc, BIT(10)),
@@ -48,6 +57,10 @@ static struct ccu_reset a31_resets[] = {
        [RST_AHB1_MMC1]         = RESET(0x2c0, BIT(9)),
        [RST_AHB1_MMC2]         = RESET(0x2c0, BIT(10)),
        [RST_AHB1_MMC3]         = RESET(0x2c0, BIT(11)),
+       [RST_AHB1_SPI0]         = RESET(0x2c0, BIT(20)),
+       [RST_AHB1_SPI1]         = RESET(0x2c0, BIT(21)),
+       [RST_AHB1_SPI2]         = RESET(0x2c0, BIT(22)),
+       [RST_AHB1_SPI3]         = RESET(0x2c0, BIT(23)),
        [RST_AHB1_OTG]          = RESET(0x2c0, BIT(24)),
        [RST_AHB1_EHCI0]        = RESET(0x2c0, BIT(26)),
        [RST_AHB1_EHCI1]        = RESET(0x2c0, BIT(27)),

diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 910275f..322d6cd 100644 (file)
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -16,6 +16,8 @@ static const struct ccu_clk_gate a64_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
+       [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_BUS_OTG]           = GATE(0x060, BIT(23)),
        [CLK_BUS_EHCI0]         = GATE(0x060, BIT(24)),
        [CLK_BUS_EHCI1]         = GATE(0x060, BIT(25)),
@@ -28,6 +30,9 @@ static const struct ccu_clk_gate a64_gates[] = {
        [CLK_BUS_UART3]         = GATE(0x06c, BIT(19)),
        [CLK_BUS_UART4]         = GATE(0x06c, BIT(20)),
 
+       [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
+       [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
+
        [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
        [CLK_USB_PHY1]          = GATE(0x0cc, BIT(9)),
        [CLK_USB_HSIC]          = GATE(0x0cc, BIT(10)),
@@ -44,6 +49,8 @@ static const struct ccu_reset a64_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
+       [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(23)),
        [RST_BUS_EHCI0]         = RESET(0x2c0, BIT(24)),
        [RST_BUS_EHCI1]         = RESET(0x2c0, BIT(25)),

diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index aec1d80..fb76aad 100644 (file)
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -13,7 +13,16 @@
 #include <dt-bindings/reset/sun9i-a80-ccu.h>
 
 static const struct ccu_clk_gate a80_gates[] = {
+       [CLK_SPI0]              = GATE(0x430, BIT(31)),
+       [CLK_SPI1]              = GATE(0x434, BIT(31)),
+       [CLK_SPI2]              = GATE(0x438, BIT(31)),
+       [CLK_SPI3]              = GATE(0x43c, BIT(31)),
+
        [CLK_BUS_MMC]           = GATE(0x580, BIT(8)),
+       [CLK_BUS_SPI0]          = GATE(0x580, BIT(20)),
+       [CLK_BUS_SPI1]          = GATE(0x580, BIT(21)),
+       [CLK_BUS_SPI2]          = GATE(0x580, BIT(22)),
+       [CLK_BUS_SPI3]          = GATE(0x580, BIT(23)),
 
        [CLK_BUS_UART0]         = GATE(0x594, BIT(16)),
        [CLK_BUS_UART1]         = GATE(0x594, BIT(17)),
@@ -25,6 +34,10 @@ static const struct ccu_clk_gate a80_gates[] = {
 
 static const struct ccu_reset a80_resets[] = {
        [RST_BUS_MMC]           = RESET(0x5a0, BIT(8)),
+       [RST_BUS_SPI0]          = RESET(0x5a0, BIT(20)),
+       [RST_BUS_SPI1]          = RESET(0x5a0, BIT(21)),
+       [RST_BUS_SPI2]          = RESET(0x5a0, BIT(22)),
+       [RST_BUS_SPI3]          = RESET(0x5a0, BIT(23)),
 
        [RST_BUS_UART0]         = RESET(0x5b4, BIT(16)),
        [RST_BUS_UART1]         = RESET(0x5b4, BIT(17)),

diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index b5a555d..36f7e14 100644 (file)
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -16,6 +16,8 @@ static struct ccu_clk_gate a83t_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
+       [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_BUS_OTG]           = GATE(0x060, BIT(24)),
        [CLK_BUS_EHCI0]         = GATE(0x060, BIT(26)),
        [CLK_BUS_EHCI1]         = GATE(0x060, BIT(27)),
@@ -27,6 +29,9 @@ static struct ccu_clk_gate a83t_gates[] = {
        [CLK_BUS_UART3]         = GATE(0x06c, BIT(19)),
        [CLK_BUS_UART4]         = GATE(0x06c, BIT(20)),
 
+       [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
+       [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
+
        [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
        [CLK_USB_PHY1]          = GATE(0x0cc, BIT(9)),
        [CLK_USB_HSIC]          = GATE(0x0cc, BIT(10)),
@@ -42,6 +47,8 @@ static struct ccu_reset a83t_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
+       [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(24)),
        [RST_BUS_EHCI0]         = RESET(0x2c0, BIT(26)),
        [RST_BUS_EHCI1]         = RESET(0x2c0, BIT(27)),

diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 416aec2..5f99ef7 100644 (file)
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -16,6 +16,8 @@ static struct ccu_clk_gate h3_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
+       [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_BUS_OTG]           = GATE(0x060, BIT(23)),
        [CLK_BUS_EHCI0]         = GATE(0x060, BIT(24)),
        [CLK_BUS_EHCI1]         = GATE(0x060, BIT(25)),
@@ -31,6 +33,9 @@ static struct ccu_clk_gate h3_gates[] = {
        [CLK_BUS_UART2]         = GATE(0x06c, BIT(18)),
        [CLK_BUS_UART3]         = GATE(0x06c, BIT(19)),
 
+       [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
+       [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
+
        [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
        [CLK_USB_PHY1]          = GATE(0x0cc, BIT(9)),
        [CLK_USB_PHY2]          = GATE(0x0cc, BIT(10)),
@@ -50,6 +55,8 @@ static struct ccu_reset h3_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
+       [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(23)),
        [RST_BUS_EHCI0]         = RESET(0x2c0, BIT(24)),
        [RST_BUS_EHCI1]         = RESET(0x2c0, BIT(25)),

diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 902612d..71f0c78 100644 (file)
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -20,6 +20,12 @@ static struct ccu_clk_gate h6_gates[] = {
        [CLK_BUS_UART1]         = GATE(0x90c, BIT(1)),
        [CLK_BUS_UART2]         = GATE(0x90c, BIT(2)),
        [CLK_BUS_UART3]         = GATE(0x90c, BIT(3)),
+
+       [CLK_SPI0]              = GATE(0x940, BIT(31)),
+       [CLK_SPI1]              = GATE(0x944, BIT(31)),
+
+       [CLK_BUS_SPI0]          = GATE(0x96c, BIT(0)),
+       [CLK_BUS_SPI1]          = GATE(0x96c, BIT(1)),
 };
 
 static struct ccu_reset h6_resets[] = {
@@ -30,6 +36,9 @@ static struct ccu_reset h6_resets[] = {
        [RST_BUS_UART1]         = RESET(0x90c, BIT(17)),
        [RST_BUS_UART2]         = RESET(0x90c, BIT(18)),
        [RST_BUS_UART3]         = RESET(0x90c, BIT(19)),
+
+       [RST_BUS_SPI0]          = RESET(0x96c, BIT(16)),
+       [RST_BUS_SPI1]          = RESET(0x96c, BIT(17)),
 };
 
 static const struct ccu_desc h6_ccu_desc = {

diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index b9457e1..9290728 100644 (file)
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -17,6 +17,10 @@ static struct ccu_clk_gate r40_gates[] = {
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
        [CLK_BUS_MMC3]          = GATE(0x060, BIT(11)),
+       [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
+       [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
+       [CLK_BUS_SPI2]          = GATE(0x060, BIT(22)),
+       [CLK_BUS_SPI3]          = GATE(0x060, BIT(23)),
        [CLK_BUS_OTG]           = GATE(0x060, BIT(25)),
        [CLK_BUS_EHCI0]         = GATE(0x060, BIT(26)),
        [CLK_BUS_EHCI1]         = GATE(0x060, BIT(27)),
@@ -34,6 +38,11 @@ static struct ccu_clk_gate r40_gates[] = {
        [CLK_BUS_UART6]         = GATE(0x06c, BIT(22)),
        [CLK_BUS_UART7]         = GATE(0x06c, BIT(23)),
 
+       [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
+       [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
+       [CLK_SPI2]              = GATE(0x0a8, BIT(31)),
+       [CLK_SPI3]              = GATE(0x0ac, BIT(31)),
+
        [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
        [CLK_USB_PHY1]          = GATE(0x0cc, BIT(9)),
        [CLK_USB_PHY2]          = GATE(0x0cc, BIT(10)),
@@ -51,6 +60,10 @@ static struct ccu_reset r40_resets[] = {
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
        [RST_BUS_MMC3]          = RESET(0x2c0, BIT(11)),
+       [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
+       [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
+       [RST_BUS_SPI2]          = RESET(0x2c0, BIT(22)),
+       [RST_BUS_SPI3]          = RESET(0x2c0, BIT(23)),
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(25)),
        [RST_BUS_EHCI0]         = RESET(0x2c0, BIT(26)),
        [RST_BUS_EHCI1]         = RESET(0x2c0, BIT(27)),

diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index c8a9027..789ac72 100644 (file)
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -16,12 +16,15 @@ static struct ccu_clk_gate v3s_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_BUS_OTG]           = GATE(0x060, BIT(24)),
 
        [CLK_BUS_UART0]         = GATE(0x06c, BIT(16)),
        [CLK_BUS_UART1]         = GATE(0x06c, BIT(17)),
        [CLK_BUS_UART2]         = GATE(0x06c, BIT(18)),
 
+       [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
+
        [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
 };
 
@@ -31,6 +34,7 @@ static struct ccu_reset v3s_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(24)),
 
        [RST_BUS_UART0]         = RESET(0x2d8, BIT(16)),