arm: dts: Add base dtsi and devkit dts for Intel N5X device

Add device tree for N5X.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <lftan.linux@gmail.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c42715e..82a0790 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -400,6 +400,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=                               \
        socfpga_cyclone5_socrates.dtb                   \
        socfpga_cyclone5_sr1500.dtb                     \
        socfpga_cyclone5_vining_fpga.dtb                \
+       socfpga_n5x_socdk.dtb                           \
        socfpga_stratix10_socdk.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \

diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
new file mode 100644 (file)
index 0000000..d377ae5
--- /dev/null
+++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ */
+
+#include "socfpga_soc64_fit-u-boot.dtsi"
+#include <dt-bindings/clock/n5x-clock.h>
+
+/{
+       memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               u-boot,dm-pre-reloc;
+       };
+
+       soc {
+               u-boot,dm-pre-reloc;
+
+               ccu: cache-controller@f7000000 {
+                       compatible = "arteris,ncore-ccu";
+                       reg = <0xf7000000 0x100900>;
+                       u-boot,dm-pre-reloc;
+               };
+
+               clocks {
+                       dram_eosc_clk: dram-eosc-clk {
+                               #clock-cells = <0>;
+                               compatible = "fixed-clock";
+                       };
+               };
+
+               memclkmgr: mem-clock-controller@f8040000 {
+                       compatible = "intel,n5x-mem-clkmgr";
+                       reg = <0xf8040000 0x1000>;
+                       #clock-cells = <0>;
+                       clocks = <&dram_eosc_clk>, <&f2s_free_clk>;
+               };
+       };
+};
+
+&clkmgr {
+       compatible = "intel,n5x-clkmgr";
+       u-boot,dm-pre-reloc;
+};
+
+&gmac0 {
+       clocks = <&clkmgr N5X_EMAC0_CLK>;
+};
+
+&gmac1 {
+       altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+       clocks = <&clkmgr N5X_EMAC1_CLK>;
+};
+
+&gmac2 {
+       altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+       clocks = <&clkmgr N5X_EMAC2_CLK>;
+};
+
+&i2c0 {
+       clocks = <&clkmgr N5X_L4_SP_CLK>;
+       reset-names = "i2c";
+};
+
+&i2c1 {
+       clocks = <&clkmgr N5X_L4_SP_CLK>;
+       reset-names = "i2c";
+};
+
+&i2c2 {
+       clocks = <&clkmgr N5X_L4_SP_CLK>;
+       reset-names = "i2c";
+};
+
+&i2c3 {
+       clocks = <&clkmgr N5X_L4_SP_CLK>;
+       reset-names = "i2c";
+};
+
+&i2c4 {
+       clocks = <&clkmgr N5X_L4_SP_CLK>;
+       reset-names = "i2c";
+};
+
+&memclkmgr {
+       u-boot,dm-pre-reloc;
+};
+
+&mmc {
+       clocks = <&clkmgr N5X_L4_MP_CLK>,
+                <&clkmgr N5X_SDMMC_CLK>;
+       resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+};
+
+&pdma {
+       clocks = <&clkmgr N5X_L4_MAIN_CLK>;
+};
+
+&porta {
+       bank-name = "porta";
+};
+
+&portb {
+       bank-name = "portb";
+};
+
+&qspi {
+       u-boot,dm-pre-reloc;
+};
+
+&rst {
+       compatible = "altr,rst-mgr";
+       altr,modrst-offset = <0x20>;
+       u-boot,dm-pre-reloc;
+};
+
+&sdr {
+       compatible = "intel,sdr-ctl-n5x";
+       resets = <&rst DDRSCH_RESET>;
+       clocks = <&memclkmgr>;
+       clock-names = "mem_clk";
+       u-boot,dm-pre-reloc;
+};
+
+&spi0 {
+       clocks = <&clkmgr N5X_L4_MAIN_CLK>;
+};
+
+&spi1 {
+       clocks = <&clkmgr N5X_L4_MAIN_CLK>;
+};
+
+&sysmgr {
+       compatible = "altr,sys-mgr", "syscon";
+       u-boot,dm-pre-reloc;
+};
+
+&timer0 {
+       clocks = <&clkmgr N5X_L4_SP_CLK>;
+};
+
+&timer1 {
+       clocks = <&clkmgr N5X_L4_SP_CLK>;
+};
+
+&timer2 {
+       clocks = <&clkmgr N5X_L4_SP_CLK>;
+};
+
+&timer3 {
+       clocks = <&clkmgr N5X_L4_SP_CLK>;
+};
+
+&uart0 {
+       clocks = <&clkmgr N5X_L4_SP_CLK>;
+       u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+       clocks = <&clkmgr N5X_L4_SP_CLK>;
+};
+
+&usb0 {
+       clocks = <&clkmgr N5X_USB_CLK>;
+       disable-over-current;
+       u-boot,dm-pre-reloc;
+};
+
+&usb1 {
+       clocks = <&clkmgr N5X_USB_CLK>;
+       u-boot,dm-pre-reloc;
+};
+
+&watchdog0 {
+       clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
+       u-boot,dm-pre-reloc;
+};
+
+&watchdog1 {
+       clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
+};
+
+&watchdog2 {
+       clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
+};
+
+&watchdog3 {
+       clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
+};

diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
new file mode 100644 (file)
index 0000000..502da36
--- /dev/null
+++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ */
+
+#include "socfpga_n5x-u-boot.dtsi"
+
+/{
+       aliases {
+               spi0 = &qspi;
+               i2c0 = &i2c1;
+       };
+
+       memory {
+               /*
+                * Memory type: DDR4 (non-interleaving mode)
+                * 16GB
+                *     <0 0x00000000 0 0x80000000>,
+                *     <4 0x80000000 3 0x80000000>;
+                *
+                * 8GB
+                *     <0 0x00000000 0 0x80000000>,
+                *     <2 0x80000000 1 0x80000000>;
+                *
+                * 4GB
+                *     <0 0x00000000 0 0x80000000>,
+                *     <1 0x80000000 0 0x80000000>;
+                *
+                * Memory type: LPDDR4 (non-interleaving mode)
+                * Total memory size 3GB, usable = 2.5GB, 0.5GB trade off for secure
+                * region.
+                */
+               reg = <0 0x00000000 0 0x60000000>,
+                         <0x10 0x00100000 0 0x40000000>;
+       };
+};
+
+&flash0 {
+       compatible = "jedec,spi-nor";
+       spi-tx-bus-width = <4>;
+       spi-rx-bus-width = <4>;
+       u-boot,dm-pre-reloc;
+};
+
+&i2c1 {
+       status = "okay";
+};
+
+&mmc {
+       drvsel = <3>;
+       smplsel = <0>;
+       u-boot,dm-pre-reloc;
+};
+
+&qspi {
+       status = "okay";
+};
+
+&watchdog0 {
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/arm/dts/socfpga_n5x_socdk.dts b/arch/arm/dts/socfpga_n5x_socdk.dts
new file mode 100644 (file)
index 0000000..915b8f6
--- /dev/null
+++ b/arch/arm/dts/socfpga_n5x_socdk.dts
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier:     GPL-2.0
+/*
+ * Copyright (C) 2020-2021, Intel Corporation
+ */
+#include "socfpga_agilex.dtsi"
+
+/ {
+       model = "eASIC N5X SoCDK";
+
+       aliases {
+               serial0 = &uart0;
+               ethernet0 = &gmac0;
+               ethernet1 = &gmac1;
+               ethernet2 = &gmac2;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory {
+               device_type = "memory";
+               /* We expect the bootloader to fill in the reg */
+               reg = <0 0 0 0>;
+       };
+
+       soc {
+               clocks {
+                       osc1 {
+                               clock-frequency = <25000000>;
+                       };
+               };
+       };
+};
+
+&gmac0 {
+       status = "okay";
+       phy-mode = "rgmii";
+       phy-handle = <&phy0>;
+       max-frame-size = <9000>;
+
+       mdio0 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "snps,dwmac-mdio";
+               phy0: ethernet-phy@0 {
+                       reg = <4>;
+
+                       txd0-skew-ps = <0>; /* -420ps */
+                       txd1-skew-ps = <0>; /* -420ps */
+                       txd2-skew-ps = <0>; /* -420ps */
+                       txd3-skew-ps = <0>; /* -420ps */
+                       rxd0-skew-ps = <420>; /* 0ps */
+                       rxd1-skew-ps = <420>; /* 0ps */
+                       rxd2-skew-ps = <420>; /* 0ps */
+                       rxd3-skew-ps = <420>; /* 0ps */
+                       txen-skew-ps = <0>; /* -420ps */
+                       txc-skew-ps = <900>; /* 0ps */
+                       rxdv-skew-ps = <420>; /* 0ps */
+                       rxc-skew-ps = <1680>; /* 780ps */
+               };
+       };
+};
+
+&gpio1 {
+       status = "okay";
+};
+
+&mmc {
+       status = "okay";
+       cap-sd-highspeed;
+       broken-cd;
+       bus-width = <4>;
+};
+
+&qspi {
+       status = "okay";
+       flash0: flash@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "mt25qu02g";
+               reg = <0>;
+               spi-max-frequency = <100000000>;
+
+               m25p,fast-read;
+               cdns,page-size = <256>;
+               cdns,block-size = <16>;
+               cdns,read-delay = <3>;
+               cdns,tshsl-ns = <50>;
+               cdns,tsd2d-ns = <50>;
+               cdns,tchsh-ns = <4>;
+               cdns,tslch-ns = <4>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       qspi_boot: partition@0 {
+                               label = "Boot and fpga data";
+                               reg = <0x0 0x034B0000>;
+                       };
+
+                       qspi_rootfs: partition@34B0000 {
+                               label = "Root Filesystem - JFFS2";
+                               reg = <0x034B0000 0x0EB50000>;
+                       };
+               };
+       };
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&usb0 {
+       status = "okay";
+};
+
+&usb1 {
+       status = "okay";
+};