-; RUN: llc -march=aarch64 < %s | FileCheck %s -check-prefix=A64
+; RUN: llc -march=aarch64 %s -o - | FileCheck %s -check-prefix=A64
define i32 @ror(i32 %a) {
entry:
%4 = or i32 %1, %3
ret i32 %4
}
-; A64-LABEL:shl_nogood: // @shl_nogood
+; A64-LABEL: shl_nogood:
; A64: sxth w8, w0
; A64-NEXT: mov w9, #172
; A64-NEXT: and w9, w8, w9
; A64-NEXT: and w8, w8, w10
; A64-NEXT: orr w0, w9, w8
; A64-NEXT: ret
-; A64-LABEL:shl_nogood2: // @shl_nogood2
+; A64-LABEL: shl_nogood2:
; A64: sxth w8, w0
; A64-NEXT: mov w9, #172
; A64-NEXT: and w9, w8, w9
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv4t-arm-none-eabi"
-; RUN: llc -march=arm < %s | FileCheck %s -check-prefix=ARM
+; RUN: llc -march=arm %s -o - | FileCheck %s -check-prefix=ARM
define i32 @ror(i32 %a) {
entry:
%4 = or i32 %1, %3
ret i32 %4
}
-; ARM-LABEL:shl_nogood:
+; ARM-LABEL: shl_nogood:
; ARM: lsl r0, r0, #16
; ARM-NEXT: mov r1, #172
; ARM-NEXT: and r1, r1, r0, asr #16
; ARM-NEXT: and r0, r2, r0, lsl r1
; ARM-NEXT: orr r0, r1, r0
; ARM-NEXT: mov pc, lr
-; ARM-LABEL:shl_nogood2:
+; ARM-LABEL: shl_nogood2:
; ARM: lsl r0, r0, #16
; ARM-NEXT: mov r1, #172
; ARM-NEXT: asr r2, r0, #16