--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cl006b_h_
+#define _cl006b_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class NV03_CHANNEL_DMA */
+#define NV03_CHANNEL_DMA (0x0000006B)
+/* NvNotification[] fields and values */
+#define NV06B_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
+/* pio method data structure */
+typedef volatile struct _cl006b_tag0 {
+ NvV32 Reserved00[0x7c0];
+} Nv06bTypedef, Nv03ChannelDma;
+#define NV06B_TYPEDEF Nv03ChannelDma
+#define nv03ChannelDma Nv03ChannelDma
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _cl006b_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cl006c_h_
+#define _cl006c_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class NV04_CHANNEL_DMA */
+#define NV04_CHANNEL_DMA (0x0000006C)
+#define NV06C_NOTIFIERS_MAXCOUNT 1
+/* NvNotification[] fields and values */
+#define NV06C_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
+#define NV06C_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
+/* pio method data structure */
+typedef volatile struct _cl006c_tag0 {
+ NvV32 Reserved00[0x7c0];
+} Nv06cTypedef, Nv04ChannelDma;
+#define NV06C_TYPEDEF Nv04ChannelDma
+/* pio flow control data structure */
+typedef volatile struct _cl006c_tag1 {
+ NvV32 Ignored00[0x010];
+ NvU32 Put; /* put offset, write only 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvV32 Ignored01[0x002];
+ NvU32 StallNotifier; /* Set stall notifier 0050-0053*/
+ NvU32 StallChannel; /* Stall the channel 0054-0057*/
+ NvV32 Ignored02[0x3EA];
+} Nv04ControlDma;
+/* obsolete stuff */
+#define NV4_CHANNEL_DMA (0x0000006C)
+#define Nv4ChannelDma Nv04ChannelDma
+#define nv4ChannelDma Nv04ChannelDma
+#define Nv4ControlDma Nv04ControlDma
+
+/* dma method descriptor format */
+#define NV06C_METHOD_ADDRESS 12:2
+#define NV06C_METHOD_SUBCHANNEL 15:13
+#define NV06C_METHOD_COUNT 28:18
+#define NV06C_OPCODE 31:29
+#define NV06C_OPCODE_METHOD (0x00000000)
+#define NV06C_OPCODE_NONINC_METHOD (0x00000002)
+/* dma data format */
+#define NV06C_DATA 31:0
+/* dma jump format */
+#define NV06C_OPCODE_JUMP (0x00000001)
+#define NV06C_JUMP_OFFSET 28:2
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _cl006c_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cl006e_h_
+#define _cl006e_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class NV10_CHANNEL_DMA */
+#define NV10_CHANNEL_DMA (0x0000006E)
+#define NV06E_NOTIFIERS_MAXCOUNT 1
+/* NvNotification[] fields and values */
+#define NV06E_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
+#define NV06E_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
+/* pio method data structure */
+typedef volatile struct _cl006e_tag0 {
+ NvV32 Reserved00[0x7c0];
+} Nv06eTypedef, Nv10ChannelDma;
+#define NV06E_TYPEDEF Nv10ChannelDma
+/* pio flow control data structure */
+typedef volatile struct _cl006e_tag1 {
+ NvV32 Ignored00[0x010];
+ NvU32 Put; /* put offset, write only 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvV32 Ignored01[0x1];
+ NvU32 SetReference; /* reference value, write only 0050-0053*/
+ NvV32 Ignored02[0x3eb];
+} Nv06eControl, Nv10ControlDma;
+/* fields and values */
+#define NV06E_NUMBER_OF_SUBCHANNELS (8)
+#define NV06E_SET_OBJECT (0x00000000)
+#define NV06E_SET_REFERENCE (0x00000050)
+
+/* dma method descriptor format */
+#define NV06E_DMA_METHOD_ADDRESS 12:2
+#define NV06E_DMA_METHOD_SUBCHANNEL 15:13
+#define NV06E_DMA_METHOD_COUNT 28:18
+#define NV06E_DMA_OPCODE 31:29
+#define NV06E_DMA_OPCODE_METHOD (0x00000000)
+#define NV06E_DMA_OPCODE_NONINC_METHOD (0x00000002)
+/* dma data format */
+#define NV06E_DMA_DATA 31:0
+/* dma jump format */
+#define NV06E_DMA_OPCODE_JUMP (0x00000001)
+#define NV06E_DMA_JUMP_OFFSET 28:2
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _cl006e_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cl206e_h_
+#define _cl206e_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class NV20_CHANNEL_DMA */
+#define NV20_CHANNEL_DMA (0x0000206E)
+/* NvNotification[] fields and values */
+#define NV206E_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
+#define NV206E_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
+/* pio method data structure */
+typedef volatile struct _cl206e_tag0 {
+ NvV32 Reserved00[0x7c0];
+} Nv206eTypedef, Nv20ChannelDma;
+#define NV206E_TYPEDEF Nv20ChannelDma
+/* pio flow control data structure */
+typedef volatile struct _cl206e_tag1 {
+ NvV32 Ignored00[0x010];
+ NvU32 Put; /* put offset, write only 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 Ignored01[0x1];
+ NvU32 SetReference; /* set reference value 0050-0053*/
+ NvU32 Ignored02[0x3];
+ NvU32 SetContextDmaSemaphore; /* set sema ctxdma, write only 0060-0063*/
+ NvU32 SetSemaphoreOffset; /* set sema offset, write only 0064-0067*/
+ NvU32 SetSemaphoreAcquire; /* set sema acquire, write only 0068-006b*/
+ NvU32 SetSemaphoreRelease; /* set sema release, write only 006c-006f*/
+ NvV32 Ignored03[0x3e4];
+} Nv206eControl, Nv20ControlDma;
+/* fields and values */
+#define NV206E_NUMBER_OF_SUBCHANNELS (8)
+#define NV206E_SET_OBJECT (0x00000000)
+#define NV206E_SET_REFERENCE (0x00000050)
+#define NV206E_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
+#define NV206E_SEMAPHORE_OFFSET (0x00000064)
+#define NV206E_SEMAPHORE_ACQUIRE (0x00000068)
+#define NV206E_SEMAPHORE_RELEASE (0x0000006c)
+#define NV206E_SUBROUTINE_STATE_RESET (0x0000009c)
+
+/* dma method descriptor format */
+#define NV206E_DMA_METHOD_ADDRESS 12:2
+#define NV206E_DMA_METHOD_SUBCHANNEL 15:13
+#define NV206E_DMA_METHOD_COUNT 28:18
+
+/* dma opcode format */
+#define NV206E_DMA_OPCODE 31:29
+#define NV206E_DMA_OPCODE_METHOD (0x00000000)
+#define NV206E_DMA_OPCODE_NONINC_METHOD (0x00000002)
+/* dma jump format */
+#define NV206E_DMA_OPCODE_JUMP (0x00000001)
+#define NV206E_DMA_JUMP_OFFSET 28:2
+
+/* dma opcode2 format */
+#define NV206E_DMA_OPCODE2 1:0
+#define NV206E_DMA_OPCODE2_NONE (0x00000000)
+/* dma jump_long format */
+#define NV206E_DMA_OPCODE2_JUMP_LONG (0x00000001)
+#define NV206E_DMA_JUMP_LONG_OFFSET 31:2
+/* dma call format */
+#define NV206E_DMA_OPCODE2_CALL (0x00000002)
+#define NV206E_DMA_CALL_OFFSET 31:2
+
+/* dma opcode3 format */
+#define NV206E_DMA_OPCODE3 17:16
+#define NV206E_DMA_OPCODE3_NONE (0x00000000)
+/* dma return format */
+#define NV206E_DMA_RETURN (0x00020000)
+#define NV206E_DMA_OPCODE3_RETURN (0x00000002)
+
+/* dma data format */
+#define NV206E_DMA_DATA 31:0
+
+/* dma nop format */
+#define NV206E_DMA_NOP (0x00000000)
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _cl206e_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cl366e_h_
+#define _cl366e_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class NV36_CHANNEL_DMA */
+#define NV36_CHANNEL_DMA (0x0000366E)
+/* NvNotification[] fields and values */
+#define NV366E_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
+#define NV366E_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
+/* pio method data structure */
+typedef volatile struct _cl366e_tag0 {
+ NvV32 Reserved00[0x7c0];
+} Nv366eTypedef, Nv36ChannelDma;
+#define NV366E_TYPEDEF Nv36ChannelDma
+/* pio flow control data structure */
+typedef volatile struct _cl366e_tag1 {
+ NvV32 Ignored00[0x010];
+ NvU32 Put; /* put offset, write only 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 Ignored01[0x1];
+ NvU32 SetReference; /* set reference value 0050-0053*/
+ NvU32 Ignored02[0x3];
+ NvU32 SetContextDmaSemaphore; /* set sema ctxdma, write only 0060-0063*/
+ NvU32 SetSemaphoreOffset; /* set sema offset, write only 0064-0067*/
+ NvU32 SetSemaphoreAcquire; /* set sema acquire, write only 0068-006b*/
+ NvU32 SetSemaphoreRelease; /* set sema release, write only 006c-006f*/
+ NvV32 Ignored03[0x3e4];
+} Nv366eControl, Nv36ControlDma;
+/* fields and values */
+#define NV366E_NUMBER_OF_SUBCHANNELS (8)
+#define NV366E_SET_OBJECT (0x00000000)
+#define NV366E_SET_REFERENCE (0x00000050)
+#define NV366E_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
+#define NV366E_SEMAPHORE_OFFSET (0x00000064)
+#define NV366E_SEMAPHORE_ACQUIRE (0x00000068)
+#define NV366E_SEMAPHORE_RELEASE (0x0000006c)
+
+/* dma method descriptor format */
+#define NV366E_DMA_METHOD_ADDRESS 12:2
+#define NV366E_DMA_METHOD_SUBCHANNEL 15:13
+#define NV366E_DMA_METHOD_COUNT 28:18
+
+/* dma opcode format */
+#define NV366E_DMA_OPCODE 31:29
+#define NV366E_DMA_OPCODE_METHOD (0x00000000)
+#define NV366E_DMA_OPCODE_NONINC_METHOD (0x00000002)
+/* dma jump format */
+#define NV366E_DMA_OPCODE_JUMP (0x00000001)
+#define NV366E_DMA_JUMP_OFFSET 28:2
+
+/* dma opcode2 format */
+#define NV366E_DMA_OPCODE2 1:0
+#define NV366E_DMA_OPCODE2_NONE (0x00000000)
+/* dma jump_long format */
+#define NV366E_DMA_OPCODE2_JUMP_LONG (0x00000001)
+#define NV366E_DMA_JUMP_LONG_OFFSET 31:2
+/* dma call format */
+#define NV366E_DMA_OPCODE2_CALL (0x00000002)
+#define NV366E_DMA_CALL_OFFSET 31:2
+
+/* dma opcode3 format */
+#define NV366E_DMA_OPCODE3 17:16
+#define NV366E_DMA_OPCODE3_NONE (0x00000000)
+/* dma return format */
+#define NV366E_DMA_RETURN (0x00020000)
+#define NV366E_DMA_OPCODE3_RETURN (0x00000002)
+
+/* dma data format */
+#define NV366E_DMA_DATA 31:0
+
+/* dma nop format */
+#define NV366E_DMA_NOP (0x00000000)
+
+/* dma set subdevice mask format */
+#define NV366E_DMA_SET_SUBDEVICE_MASK (0x00010000)
+#define NV366E_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NV366E_DMA_OPCODE3_SET_SUBDEVICE_MASK (0x00000001)
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _cl366e_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cl406e_h_
+#define _cl406e_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class NV40_CHANNEL_DMA */
+#define NV40_CHANNEL_DMA (0x0000406E)
+
+/* event values */
+#define NV406E_NOTIFIERS_RC (0)
+#define NV406E_NOTIFIERS_SW (1)
+#define NV406E_NOTIFIERS_MAXCOUNT (2)
+
+/* NvNotification[] fields and values */
+#define NV406E_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
+#define NV406E_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
+/* pio method data structure */
+typedef volatile struct _cl406e_tag0 {
+ NvV32 Reserved00[0x7c0];
+} Nv406eTypedef, Nv40ChannelDma;
+#define NV406E_TYPEDEF Nv40ChannelDma
+/* pio flow control data structure */
+typedef volatile struct _cl406e_tag1 {
+ NvV32 Ignored00[0x010];
+ NvU32 Put; /* put offset, write only 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 Ignored01[0x1];
+ NvU32 SetReference; /* set reference value 0050-0053*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0054-0057*/
+ NvU32 Ignored02[0x2];
+ NvU32 SetContextDmaSemaphore; /* set sema ctxdma, write only 0060-0063*/
+ NvU32 SetSemaphoreOffset; /* set sema offset, write only 0064-0067*/
+ NvU32 SetSemaphoreAcquire; /* set sema acquire, write only 0068-006b*/
+ NvU32 SetSemaphoreRelease; /* set sema release, write only 006c-006f*/
+ NvV32 Ignored03[0x3e4];
+} Nv406eControl, Nv40ControlDma;
+/* fields and values */
+#define NV406E_NUMBER_OF_SUBCHANNELS (8)
+#define NV406E_SET_OBJECT (0x00000000)
+#define NV406E_SET_REFERENCE (0x00000050)
+#define NV406E_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
+#define NV406E_SEMAPHORE_OFFSET (0x00000064)
+#define NV406E_SEMAPHORE_ACQUIRE (0x00000068)
+#define NV406E_SEMAPHORE_RELEASE (0x0000006c)
+
+/* dma method descriptor format */
+#define NV406E_DMA_METHOD_ADDRESS 12:2
+#define NV406E_DMA_METHOD_SUBCHANNEL 15:13
+#define NV406E_DMA_METHOD_COUNT 28:18
+
+/* dma opcode format */
+#define NV406E_DMA_OPCODE 31:29
+#define NV406E_DMA_OPCODE_METHOD (0x00000000)
+#define NV406E_DMA_OPCODE_NONINC_METHOD (0x00000002)
+/* dma jump format */
+#define NV406E_DMA_OPCODE_JUMP (0x00000001)
+#define NV406E_DMA_JUMP_OFFSET 28:2
+
+/* dma opcode2 format */
+#define NV406E_DMA_OPCODE2 1:0
+#define NV406E_DMA_OPCODE2_NONE (0x00000000)
+/* dma jump_long format */
+#define NV406E_DMA_OPCODE2_JUMP_LONG (0x00000001)
+#define NV406E_DMA_JUMP_LONG_OFFSET 31:2
+/* dma call format */
+#define NV406E_DMA_OPCODE2_CALL (0x00000002)
+#define NV406E_DMA_CALL_OFFSET 31:2
+
+/* dma opcode3 format */
+#define NV406E_DMA_OPCODE3 17:16
+#define NV406E_DMA_OPCODE3_NONE (0x00000000)
+/* dma return format */
+#define NV406E_DMA_RETURN (0x00020000)
+#define NV406E_DMA_OPCODE3_RETURN (0x00000002)
+
+/* dma data format */
+#define NV406E_DMA_DATA 31:0
+
+/* dma nop format */
+#define NV406E_DMA_NOP (0x00000000)
+
+/* dma set subdevice mask format */
+#define NV406E_DMA_SET_SUBDEVICE_MASK (0x00010000)
+#define NV406E_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NV406E_DMA_OPCODE3_SET_SUBDEVICE_MASK (0x00000001)
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _cl406e_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cl446e_h_
+#define _cl446e_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class NV44_CHANNEL_DMA */
+#define NV44_CHANNEL_DMA (0x0000446E)
+/* NvNotification[] fields and values */
+#define NV446E_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
+#define NV446E_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
+/* pio method data structure */
+typedef volatile struct _cl446e_tag0 {
+ NvV32 Reserved00[0x7c0];
+} Nv446eTypedef, Nv44ChannelDma;
+#define NV446E_TYPEDEF Nv44ChannelDma
+/* pio flow control data structure */
+typedef volatile struct _cl446e_tag1 {
+ NvV32 Ignored00[0x010];
+ NvU32 Put; /* put offset, write only 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 Ignored01[0x1];
+ NvU32 SetReference; /* set reference value 0050-0053*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0054-0057*/
+ NvU32 Ignored02[0x2];
+ NvU32 SetContextDmaSemaphore; /* set sema ctxdma, write only 0060-0063*/
+ NvU32 SetSemaphoreOffset; /* set sema offset, write only 0064-0067*/
+ NvU32 SetSemaphoreAcquire; /* set sema acquire, write only 0068-006b*/
+ NvU32 SetSemaphoreRelease; /* set sema release, write only 006c-006f*/
+ NvV32 Ignored03[0x4];
+ NvU32 Yield; /* engine yield, write only 0080-0083*/
+ NvV32 Ignored04[0x3df];
+} Nv446eControl, Nv44ControlDma;
+/* fields and values */
+#define NV446E_NUMBER_OF_SUBCHANNELS (8)
+#define NV446E_SET_OBJECT (0x00000000)
+#define NV446E_SET_REFERENCE (0x00000050)
+#define NV446E_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
+#define NV446E_SEMAPHORE_OFFSET (0x00000064)
+#define NV446E_SEMAPHORE_ACQUIRE (0x00000068)
+#define NV446E_SEMAPHORE_RELEASE (0x0000006c)
+#define NV446E_YIELD (0x00000080)
+
+/* dma method descriptor format */
+#define NV446E_DMA_METHOD_ADDRESS 12:2
+#define NV446E_DMA_METHOD_SUBCHANNEL 15:13
+#define NV446E_DMA_METHOD_COUNT 28:18
+
+/* dma opcode format */
+#define NV446E_DMA_OPCODE 31:29
+#define NV446E_DMA_OPCODE_METHOD (0x00000000)
+#define NV446E_DMA_OPCODE_NONINC_METHOD (0x00000002)
+/* dma jump format */
+#define NV446E_DMA_OPCODE_JUMP (0x00000001)
+#define NV446E_DMA_JUMP_OFFSET 28:2
+
+/* dma opcode2 format */
+#define NV446E_DMA_OPCODE2 1:0
+#define NV446E_DMA_OPCODE2_NONE (0x00000000)
+/* dma jump_long format */
+#define NV446E_DMA_OPCODE2_JUMP_LONG (0x00000001)
+#define NV446E_DMA_JUMP_LONG_OFFSET 31:2
+/* dma call format */
+#define NV446E_DMA_OPCODE2_CALL (0x00000002)
+#define NV446E_DMA_CALL_OFFSET 31:2
+
+/* dma opcode3 format */
+#define NV446E_DMA_OPCODE3 17:16
+#define NV446E_DMA_OPCODE3_NONE (0x00000000)
+/* dma return format */
+#define NV446E_DMA_RETURN (0x00020000)
+#define NV446E_DMA_OPCODE3_RETURN (0x00000002)
+
+/* dma data format */
+#define NV446E_DMA_DATA 31:0
+
+/* dma nop format */
+#define NV446E_DMA_NOP (0x00000000)
+
+/* dma set subdevice mask format */
+#define NV446E_DMA_SET_SUBDEVICE_MASK (0x00010000)
+#define NV446E_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NV446E_DMA_OPCODE3_SET_SUBDEVICE_MASK (0x00000001)
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _cl446e_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cl506f_h_
+#define _cl506f_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class NV50_CHANNEL_GPFIFO */
+#define NV50_CHANNEL_GPFIFO (0x0000506F)
+
+/* NvNotification[] elements */
+#define NV506F_NOTIFIERS_RC (0)
+#define NV506F_NOTIFIERS_SW (1)
+#define NV506F_NOTIFIERS_GR_DEBUG_INTR (2)
+#define NV506F_NOTIFIERS_MAXCOUNT (3)
+
+/* NvNotification[] fields and values */
+#define NV506f_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
+#define NV506f_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
+/* pio method data structure */
+typedef volatile struct _cl506f_tag0 {
+ NvV32 Reserved00[0x7c0];
+} Nv506fTypedef, Nv50ChannelGPFifo;
+#define NV506F_TYPEDEF Nv50ChannelGPFifo
+/* pio flow control data structure */
+typedef volatile struct _cl506f_tag1 {
+ NvU32 Ignored00[0x010]; /* 0000-0039*/
+ NvU32 Put; /* put offset, read/write 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 PutHi; /* high order put offset bits 004c-004f*/
+ NvU32 SetReference; /* set reference value 0050-0053*/
+ NvU32 Ignored02[0x001]; /* 0054-0057*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
+ NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
+ NvU32 GetHi; /* high order get offset bits 0060-0063*/
+ NvU32 Ignored03[0x007]; /* 0064-007f*/
+ NvU32 Yield; /* engine yield, write only 0080-0083*/
+ NvU32 Ignored04[0x001]; /* 0084-0087*/
+ NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
+ NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
+ NvU32 Ignored05[0x3dc];
+} Nv506fControl, Nv50ControlGPFifo;
+/* fields and values */
+#define NV506F_NUMBER_OF_SUBCHANNELS (8)
+#define NV506F_SET_OBJECT (0x00000000)
+#define NV506F_SET_REFERENCE (0x00000050)
+#define NV506F_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
+#define NV506F_SEMAPHORE_OFFSET (0x00000064)
+#define NV506F_SEMAPHORE_ACQUIRE (0x00000068)
+#define NV506F_SEMAPHORE_RELEASE (0x0000006c)
+#define NV506F_YIELD (0x00000080)
+
+//
+// GPFIFO entry format
+//
+#define NV506F_GP_ENTRY__SIZE 8
+#define NV506F_GP_ENTRY0_DISABLE 0:0
+#define NV506F_GP_ENTRY0_DISABLE_NOT 0x00000000
+#define NV506F_GP_ENTRY0_DISABLE_SKIP 0x00000001
+#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH 1:1
+#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH_FALSE 0x00000000
+#define NV506F_GP_ENTRY0_NO_CONTEXT_SWITCH_TRUE 0x00000001
+#define NV506F_GP_ENTRY0_GET 31:2
+#define NV506F_GP_ENTRY1_GET_HI 7:0
+#define NV506F_GP_ENTRY1_PRIV 8:8
+#define NV506F_GP_ENTRY1_PRIV_USER 0x00000000
+#define NV506F_GP_ENTRY1_PRIV_KERNEL 0x00000001
+#define NV506F_GP_ENTRY1_LEVEL 9:9
+#define NV506F_GP_ENTRY1_LEVEL_MAIN 0x00000000
+#define NV506F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
+#define NV506F_GP_ENTRY1_LENGTH 31:10
+
+/* dma method descriptor formats */
+#define NV506F_DMA_PRIMARY_OPCODE 1:0
+#define NV506F_DMA_PRIMARY_OPCODE_USES_SECONDARY (0x00000000)
+#define NV506F_DMA_PRIMARY_OPCODE_RESERVED (0x00000003)
+#define NV506F_DMA_METHOD_ADDRESS 12:2
+#define NV506F_DMA_METHOD_SUBCHANNEL 15:13
+#define NV506F_DMA_TERT_OP 17:16
+#define NV506F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
+#define NV506F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
+#define NV506F_DMA_TERT_OP_GRP0_DOUBLE_HEADER (0x00000003)
+#define NV506F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
+#define NV506F_DMA_TERT_OP_GRP2_RESERVED01 (0x00000001)
+#define NV506F_DMA_TERT_OP_GRP2_RESERVED10 (0x00000002)
+#define NV506F_DMA_TERT_OP_GRP2_RESERVED11 (0x00000003)
+#define NV506F_DMA_METHOD_COUNT 28:18
+#define NV506F_DMA_SEC_OP 31:29
+#define NV506F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
+#define NV506F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
+#define NV506F_DMA_SEC_OP_GRP3_RESERVED (0x00000003)
+#define NV506F_DMA_SEC_OP_GRP4_RESERVED (0x00000004)
+#define NV506F_DMA_SEC_OP_GRP5_RESERVED (0x00000005)
+#define NV506F_DMA_SEC_OP_GRP6_RESERVED (0x00000006)
+#define NV506F_DMA_SEC_OP_GRP7_RESERVED (0x00000007)
+#define NV506F_DMA_LONG_COUNT 31:0
+/* dma legacy method descriptor format */
+#define NV506F_DMA_OPCODE2 1:0
+#define NV506F_DMA_OPCODE2_NONE (0x00000000)
+#define NV506F_DMA_OPCODE 31:29
+#define NV506F_DMA_OPCODE_METHOD (0x00000000)
+#define NV506F_DMA_OPCODE_NONINC_METHOD (0x00000002)
+#define NV506F_DMA_OPCODE3_NONE (0x00000000)
+/* dma data format */
+#define NV506F_DMA_DATA 31:0
+/* dma double header descriptor format */
+#define NV506F_DMA_DH_OPCODE2 1:0
+#define NV506F_DMA_DH_OPCODE2_NONE (0x00000000)
+#define NV506F_DMA_DH_METHOD_ADDRESS 12:2
+#define NV506F_DMA_DH_METHOD_SUBCHANNEL 15:13
+#define NV506F_DMA_DH_OPCODE3 17:16
+#define NV506F_DMA_DH_OPCODE3_DOUBLE_HEADER (0x00000003)
+#define NV506F_DMA_DH_OPCODE 31:29
+#define NV506F_DMA_DH_OPCODE_METHOD (0x00000000)
+/* dma double header method count format */
+#define NV506F_DMA_DH_METHOD_COUNT 23:0
+/* dma double header data format */
+#define NV506F_DMA_DH_DATA 31:0
+/* dma nop format */
+#define NV506F_DMA_NOP (0x00000000)
+/* dma set subdevice mask format */
+#define NV506F_DMA_SET_SUBDEVICE_MASK (0x00010000)
+#define NV506F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NV506F_DMA_OPCODE3 17:16
+#define NV506F_DMA_OPCODE3_SET_SUBDEVICE_MASK (0x00000001)
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _cl506f_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cl826f_h_
+#define _cl826f_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class G82_CHANNEL_GPFIFO */
+#define G82_CHANNEL_GPFIFO (0x0000826F)
+
+/* NvNotification[] indexes */
+/* channel id returned in index 0 at alloc time */
+#define NV826F_NOTIFIERS_GET_CHANNEL_ID_INDEX (0)
+#define NV826F_NOTIFIERS_GET_CHANNEL_ID_INFO32_ID 31:0
+/* RC error occurring in channel updates index 0 */
+#define NV826F_NOTIFIERS_ROBUST_CHANNEL_ERROR_INDEX (0)
+#define NV826F_NOTIFIERS_ROBUST_CHANNEL_ERROR_INFO32_ERRTYPE 31:0
+#define NV826F_NOTIFIERS_ROBUST_CHANNEL_ERROR_STATUS 15:0
+#define NV826F_NOTIFIERS_ROBUST_CHANNEL_ERROR_STATUS_ERROR 0xFFFF
+#define NV826F_NOTIFIERS_UNUSED (1)
+#define NV826F_NOTIFIERS_GR_DEBUG_INTR (2)
+#define NV826F_NOTIFIERS_MAXCOUNT (3)
+
+/* NvNotification[] fields and values */
+#define NV826F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
+#define NV826F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
+/* pio method data structure */
+typedef volatile struct _cl826f_tag0 {
+ NvV32 Reserved00[0x7c0];
+} Nv826fTypedef, G82ChannelGPFifo;
+#define NV826F_TYPEDEF G82ChannelGPFifo
+/* dma flow control data structure */
+typedef volatile struct _cl826f_tag1 {
+ NvU32 Ignored00[0x010]; /* 0000-0043*/
+ NvU32 Put; /* put offset, read/write 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 PutHi; /* high order put offset bits 004c-004f*/
+ NvU32 SetReference; /* set reference value 0050-0053*/
+ NvU32 Ignored02[0x001]; /* 0054-0057*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
+ NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
+ NvU32 GetHi; /* high order get offset bits 0060-0063*/
+ NvU32 Ignored03[0x007]; /* 0064-007f*/
+ NvU32 Yield; /* engine yield, write only 0080-0083*/
+ NvU32 Ignored04[0x001]; /* 0084-0087*/
+ NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
+ NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
+ NvU32 Ignored05[0x3dc];
+} Nv826fControl, G82ControlGPFifo;
+/* fields and values */
+#define NV826F_NUMBER_OF_SUBCHANNELS (8)
+#define NV826F_SET_OBJECT (0x00000000)
+#define NV826F_SEMAPHOREA (0x00000010)
+#define NV826F_SEMAPHOREA_OFFSET_UPPER 7:0
+#define NV826F_SEMAPHOREB (0x00000014)
+#define NV826F_SEMAPHOREB_OFFSET_LOWER 31:00
+#define NV826F_SEMAPHOREC (0x00000018)
+#define NV826F_SEMAPHOREC_PAYLOAD 31:0
+#define NV826F_SEMAPHORED (0x0000001C)
+#define NV826F_SEMAPHORED_OPERATION 2:0
+#define NV826F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
+#define NV826F_SEMAPHORED_OPERATION_RELEASE 0x00000002
+#define NV826F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
+#define NV826F_NON_STALLED_INTERRUPT (0x00000020)
+#define NV826F_FB_FLUSH (0x00000024)
+#define NV826F_SET_REFERENCE (0x00000050)
+#define NV826F_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
+#define NV826F_SEMAPHORE_OFFSET (0x00000064)
+#define NV826F_SEMAPHORE_ACQUIRE (0x00000068)
+#define NV826F_SEMAPHORE_RELEASE (0x0000006c)
+#define NV826F_YIELD (0x00000080)
+#define NV826F_SWITCH_NO_WAIT (0x00000084)
+
+
+/* GPFIFO entry format */
+#define NV826F_GP_ENTRY__SIZE 8
+#define NV826F_GP_ENTRY0_DISABLE 0:0
+#define NV826F_GP_ENTRY0_DISABLE_NOT 0x00000000
+#define NV826F_GP_ENTRY0_DISABLE_SKIP 0x00000001
+#define NV826F_GP_ENTRY0_NO_CONTEXT_SWITCH 1:1
+#define NV826F_GP_ENTRY0_NO_CONTEXT_SWITCH_FALSE 0x00000000
+#define NV826F_GP_ENTRY0_NO_CONTEXT_SWITCH_TRUE 0x00000001
+#define NV826F_GP_ENTRY0_GET 31:2
+#define NV826F_GP_ENTRY1_GET_HI 7:0
+#define NV826F_GP_ENTRY1_PRIV 8:8
+#define NV826F_GP_ENTRY1_PRIV_USER 0x00000000
+#define NV826F_GP_ENTRY1_PRIV_KERNEL 0x00000001
+#define NV826F_GP_ENTRY1_LEVEL 9:9
+#define NV826F_GP_ENTRY1_LEVEL_MAIN 0x00000000
+#define NV826F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
+#define NV826F_GP_ENTRY1_LENGTH 31:10
+
+/* dma method descriptor formats */
+#define NV826F_DMA_PRIMARY_OPCODE 1:0
+#define NV826F_DMA_PRIMARY_OPCODE_USES_SECONDARY (0x00000000)
+#define NV826F_DMA_PRIMARY_OPCODE_RESERVED (0x00000003)
+#define NV826F_DMA_METHOD_ADDRESS 12:2
+#define NV826F_DMA_METHOD_SUBCHANNEL 15:13
+#define NV826F_DMA_TERT_OP 17:16
+#define NV826F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
+#define NV826F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
+#define NV826F_DMA_TERT_OP_GRP0_DOUBLE_HEADER (0x00000003)
+#define NV826F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
+#define NV826F_DMA_TERT_OP_GRP2_RESERVED01 (0x00000001)
+#define NV826F_DMA_TERT_OP_GRP2_RESERVED10 (0x00000002)
+#define NV826F_DMA_TERT_OP_GRP2_RESERVED11 (0x00000003)
+#define NV826F_DMA_METHOD_COUNT 28:18
+#define NV826F_DMA_SEC_OP 31:29
+#define NV826F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
+#define NV826F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
+#define NV826F_DMA_SEC_OP_GRP3_RESERVED (0x00000003)
+#define NV826F_DMA_SEC_OP_GRP4_RESERVED (0x00000004)
+#define NV826F_DMA_SEC_OP_GRP5_RESERVED (0x00000005)
+#define NV826F_DMA_SEC_OP_GRP6_RESERVED (0x00000006)
+#define NV826F_DMA_SEC_OP_GRP7_RESERVED (0x00000007)
+#define NV826F_DMA_LONG_COUNT 31:0
+/* dma legacy method descriptor format */
+#define NV826F_DMA_OPCODE2 1:0
+#define NV826F_DMA_OPCODE2_NONE (0x00000000)
+#define NV826F_DMA_OPCODE 31:29
+#define NV826F_DMA_OPCODE_METHOD (0x00000000)
+#define NV826F_DMA_OPCODE_NONINC_METHOD (0x00000002)
+#define NV826F_DMA_OPCODE3_NONE (0x00000000)
+/* dma data format */
+#define NV826F_DMA_DATA 31:0
+/* dma double header descriptor format */
+#define NV826F_DMA_DH_OPCODE2 1:0
+#define NV826F_DMA_DH_OPCODE2_NONE (0x00000000)
+#define NV826F_DMA_DH_METHOD_ADDRESS 12:2
+#define NV826F_DMA_DH_METHOD_SUBCHANNEL 15:13
+#define NV826F_DMA_DH_OPCODE3 17:16
+#define NV826F_DMA_DH_OPCODE3_DOUBLE_HEADER (0x00000003)
+#define NV826F_DMA_DH_OPCODE 31:29
+#define NV826F_DMA_DH_OPCODE_METHOD (0x00000000)
+/* dma double header method count format */
+#define NV826F_DMA_DH_METHOD_COUNT 23:0
+/* dma double header data format */
+#define NV826F_DMA_DH_DATA 31:0
+/* dma nop format */
+#define NV826F_DMA_NOP (0x00000000)
+/* dma set subdevice mask format */
+#define NV826F_DMA_SET_SUBDEVICE_MASK (0x00010000)
+#define NV826F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NV826F_DMA_OPCODE3 17:16
+#define NV826F_DMA_OPCODE3_SET_SUBDEVICE_MASK (0x00000001)
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _cl826f_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cl866f_h_
+#define _cl866f_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class GT21A_CHANNEL_GPFIFO */
+#define GT21A_CHANNEL_GPFIFO (0x0000866F)
+
+/* NvNotification[] elements */
+#define NV866F_NOTIFIERS_RC (0)
+#define NV866F_NOTIFIERS_SW (1)
+#define NV866F_NOTIFIERS_GR_DEBUG_INTR (2)
+#define NV866F_NOTIFIERS_MAXCOUNT (3)
+
+/* NvNotification[] fields and values */
+#define NV866f_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
+#define NV866f_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
+/* pio method data structure */
+typedef volatile struct _cl866f_tag0 {
+ NvV32 Reserved00[0x7c0];
+} Nv866fTypedef, G84ChannelGPFifo;
+#define NV866F_TYPEDEF G84ChannelGPFifo
+/* dma flow control data structure */
+typedef volatile struct _cl866f_tag1 {
+ NvU32 Ignored00[0x010]; /* 0000-0043*/
+ NvU32 Put; /* put offset, read/write 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 PutHi; /* high order put offset bits 004c-004f*/
+ NvU32 SetReference; /* set reference value 0050-0053*/
+ NvU32 Ignored02[0x001]; /* 0054-0057*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
+ NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
+ NvU32 GetHi; /* high order get offset bits 0060-0063*/
+ NvU32 Ignored03[0x007]; /* 0064-007f*/
+ NvU32 Yield; /* engine yield, write only 0080-0083*/
+ NvU32 Ignored04[0x001]; /* 0084-0087*/
+ NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
+ NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
+ NvU32 Ignored05[0x3dc];
+} Nv866fControl, G84ControlGPFifo;
+/* fields and values */
+#define NV866F_NUMBER_OF_SUBCHANNELS (8)
+#define NV866F_SET_OBJECT (0x00000000)
+#define NV866F_SEMAPHOREA (0x00000010)
+#define NV866F_SEMAPHOREA_OFFSET_UPPER 7:0
+#define NV866F_SEMAPHOREB (0x00000014)
+#define NV866F_SEMAPHOREB_OFFSET_LOWER 31:00
+#define NV866F_SEMAPHOREC (0x00000018)
+#define NV866F_SEMAPHOREC_PAYLOAD 31:0
+#define NV866F_SEMAPHORED (0x0000001C)
+#define NV866F_SEMAPHORED_OPERATION 3:0
+#define NV866F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
+#define NV866F_SEMAPHORED_OPERATION_RELEASE 0x00000002
+#define NV866F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
+#define NV866F_NON_STALLED_INTERRUPT (0x00000020)
+#define NV866F_FB_FLUSH (0x00000024)
+#define NV866F_MEM_OP_A (0x00000028)
+#define NV866F_MEM_OP_A_FLUSH_VIRTUAL_BASE_ADDR 31:0
+#define NV866F_MEM_OP_B (0x0000002C)
+#define NV866F_MEM_OP_B_OPERATION 31:29
+#define NV866F_MEM_OP_B_OPERATION_EVICT (0x00000000)
+#define NV866F_MEM_OP_B_OPERATION_CLEAN (0x00000001)
+#define NV866F_MEM_OP_B_OPERATION_INVALIDATE (0x00000002)
+#define NV866F_MEM_OP_B_FLUSH_ALL 28:28
+#define NV866F_MEM_OP_B_FLUSH_ALL_DISABLED (0x00000000)
+#define NV866F_MEM_OP_B_FLUSH_ALL_ENABLED (0x00000001)
+#define NV866F_MEM_OP_B_NUM_LINES 27:0
+#define NV866F_SYSMEM_FLUSH_CTXDMA (0x00000030)
+#define NV866F_SYSMEM_FLUSH_CTXDMA_HANDLE 31:0
+#define NV866F_SET_REFERENCE (0x00000050)
+#define NV866F_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
+#define NV866F_SEMAPHORE_OFFSET (0x00000064)
+#define NV866F_SEMAPHORE_ACQUIRE (0x00000068)
+#define NV866F_SEMAPHORE_RELEASE (0x0000006c)
+#define NV866F_YIELD (0x00000080)
+#define NV866F_SWITCH_NO_WAIT (0x00000084)
+
+//
+// GPFIFO entry format
+//
+#define NV866F_GP_ENTRY__SIZE 8
+#define NV866F_GP_ENTRY0_DISABLE 0:0
+#define NV866F_GP_ENTRY0_DISABLE_NOT 0x00000000
+#define NV866F_GP_ENTRY0_DISABLE_SKIP 0x00000001
+#define NV866F_GP_ENTRY0_NO_CONTEXT_SWITCH 1:1
+#define NV866F_GP_ENTRY0_NO_CONTEXT_SWITCH_FALSE 0x00000000
+#define NV866F_GP_ENTRY0_NO_CONTEXT_SWITCH_TRUE 0x00000001
+#define NV866F_GP_ENTRY0_GET 31:2
+#define NV866F_GP_ENTRY1_GET_HI 7:0
+#define NV866F_GP_ENTRY1_PRIV 8:8
+#define NV866F_GP_ENTRY1_PRIV_USER 0x00000000
+#define NV866F_GP_ENTRY1_PRIV_KERNEL 0x00000001
+#define NV866F_GP_ENTRY1_LEVEL 9:9
+#define NV866F_GP_ENTRY1_LEVEL_MAIN 0x00000000
+#define NV866F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
+#define NV866F_GP_ENTRY1_LENGTH 31:10
+
+/* dma method descriptor formats */
+#define NV866F_DMA_PRIMARY_OPCODE 1:0
+#define NV866F_DMA_PRIMARY_OPCODE_USES_SECONDARY (0x00000000)
+#define NV866F_DMA_PRIMARY_OPCODE_RESERVED (0x00000003)
+#define NV866F_DMA_METHOD_ADDRESS 12:2
+#define NV866F_DMA_METHOD_SUBCHANNEL 15:13
+#define NV866F_DMA_TERT_OP 17:16
+#define NV866F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
+#define NV866F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
+#define NV866F_DMA_TERT_OP_GRP0_DOUBLE_HEADER (0x00000003)
+#define NV866F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
+#define NV866F_DMA_TERT_OP_GRP2_RESERVED01 (0x00000001)
+#define NV866F_DMA_TERT_OP_GRP2_RESERVED10 (0x00000002)
+#define NV866F_DMA_TERT_OP_GRP2_RESERVED11 (0x00000003)
+#define NV866F_DMA_METHOD_COUNT 28:18
+#define NV866F_DMA_SEC_OP 31:29
+#define NV866F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
+#define NV866F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
+#define NV866F_DMA_SEC_OP_GRP3_RESERVED (0x00000003)
+#define NV866F_DMA_SEC_OP_GRP4_RESERVED (0x00000004)
+#define NV866F_DMA_SEC_OP_GRP5_RESERVED (0x00000005)
+#define NV866F_DMA_SEC_OP_GRP6_RESERVED (0x00000006)
+#define NV866F_DMA_SEC_OP_GRP7_RESERVED (0x00000007)
+#define NV866F_DMA_LONG_COUNT 31:0
+/* dma legacy method descriptor format */
+#define NV866F_DMA_OPCODE2 1:0
+#define NV866F_DMA_OPCODE2_NONE (0x00000000)
+#define NV866F_DMA_OPCODE 31:29
+#define NV866F_DMA_OPCODE_METHOD (0x00000000)
+#define NV866F_DMA_OPCODE_NONINC_METHOD (0x00000002)
+#define NV866F_DMA_OPCODE3_NONE (0x00000000)
+/* dma data format */
+#define NV866F_DMA_DATA 31:0
+/* dma double header descriptor format */
+#define NV866F_DMA_DH_OPCODE2 1:0
+#define NV866F_DMA_DH_OPCODE2_NONE (0x00000000)
+#define NV866F_DMA_DH_METHOD_ADDRESS 12:2
+#define NV866F_DMA_DH_METHOD_SUBCHANNEL 15:13
+#define NV866F_DMA_DH_OPCODE3 17:16
+#define NV866F_DMA_DH_OPCODE3_DOUBLE_HEADER (0x00000003)
+#define NV866F_DMA_DH_OPCODE 31:29
+#define NV866F_DMA_DH_OPCODE_METHOD (0x00000000)
+/* dma double header method count format */
+#define NV866F_DMA_DH_METHOD_COUNT 23:0
+/* dma double header data format */
+#define NV866F_DMA_DH_DATA 31:0
+/* dma nop format */
+#define NV866F_DMA_NOP (0x00000000)
+/* dma set subdevice mask format */
+#define NV866F_DMA_SET_SUBDEVICE_MASK (0x00010000)
+#define NV866F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NV866F_DMA_OPCODE3 17:16
+#define NV866F_DMA_OPCODE3_SET_SUBDEVICE_MASK (0x00000001)
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _cl866f_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cl906f_h_
+#define _cl906f_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class GF100_CHANNEL_GPFIFO */
+/*
+ * Documentation for GF100_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
+ * chapter "User Control Registers". It is documented as device NV_UDMA.
+ * The GPFIFO format itself is also documented in dev_pbdma.ref,
+ * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
+ * chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
+ *
+ */
+#define GF100_CHANNEL_GPFIFO (0x0000906F)
+
+/* pio method data structure */
+typedef volatile struct _cl906f_tag0 {
+ NvV32 Reserved00[0x7c0];
+} Nv906fTypedef, GF100ChannelGPFifo;
+#define NV906F_TYPEDEF GF100ChannelGPFifo
+/* dma flow control data structure */
+typedef volatile struct _cl906f_tag1 {
+ NvU32 Ignored00[0x010]; /* 0000-0043*/
+ NvU32 Put; /* put offset, read/write 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 PutHi; /* high order put offset bits 004c-004f*/
+ NvU32 SetReferenceThreshold; /* set reference value threshold 0050-0053*/
+ NvU32 Ignored01[0x001]; /* 0054-0057*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
+ NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
+ NvU32 GetHi; /* high order get offset bits 0060-0063*/
+ NvU32 Ignored02[0x007]; /* 0064-007f*/
+ NvU32 Ignored03; /* used to be engine yield 0080-0083*/
+ NvU32 Ignored04[0x001]; /* 0084-0087*/
+ NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
+ NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
+ NvU32 Ignored05[0x3dc];
+} Nv906fControl, GF100ControlGPFifo;
+/* fields and values */
+#define NV906F_NUMBER_OF_SUBCHANNELS (8)
+#define NV906F_SET_OBJECT (0x00000000)
+#define NV906F_SET_OBJECT_NVCLASS 15:0
+#define NV906F_SET_OBJECT_ENGINE 20:16
+#define NV906F_SET_OBJECT_ENGINE_SW 0x0000001f
+#define NV906F_ILLEGAL (0x00000004)
+#define NV906F_ILLEGAL_HANDLE 31:0
+#define NV906F_NOP (0x00000008)
+#define NV906F_NOP_HANDLE 31:0
+#define NV906F_SEMAPHOREA (0x00000010)
+#define NV906F_SEMAPHOREA_OFFSET_UPPER 7:0
+#define NV906F_SEMAPHOREB (0x00000014)
+#define NV906F_SEMAPHOREB_OFFSET_LOWER 31:2
+#define NV906F_SEMAPHOREC (0x00000018)
+#define NV906F_SEMAPHOREC_PAYLOAD 31:0
+#define NV906F_SEMAPHORED (0x0000001C)
+#define NV906F_SEMAPHORED_OPERATION 3:0
+#define NV906F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
+#define NV906F_SEMAPHORED_OPERATION_RELEASE 0x00000002
+#define NV906F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
+#define NV906F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
+#define NV906F_SEMAPHORED_ACQUIRE_SWITCH 12:12
+#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
+#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
+#define NV906F_SEMAPHORED_RELEASE_WFI 20:20
+#define NV906F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
+#define NV906F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
+#define NV906F_SEMAPHORED_RELEASE_SIZE 24:24
+#define NV906F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
+#define NV906F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
+#define NV906F_NON_STALL_INTERRUPT (0x00000020)
+#define NV906F_NON_STALL_INTERRUPT_HANDLE 31:0
+#define NV906F_FB_FLUSH (0x00000024)
+#define NV906F_FB_FLUSH_HANDLE 31:0
+#define NV906F_MEM_OP_A (0x00000028)
+#define NV906F_MEM_OP_A_OPERAND_LOW 31:2
+#define NV906F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2
+#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30
+#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000
+#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002
+#define NV906F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003
+#define NV906F_MEM_OP_B (0x0000002c)
+#define NV906F_MEM_OP_B_OPERAND_HIGH 7:0
+#define NV906F_MEM_OP_B_OPERATION 31:27
+#define NV906F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005
+#define NV906F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006
+#define NV906F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009
+#define NV906F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
+#define NV906F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
+#define NV906F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
+#define NV906F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010
+#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0
+#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000
+#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001
+#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1
+#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000
+#define NV906F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001
+#define NV906F_SET_REFERENCE (0x00000050)
+#define NV906F_SET_REFERENCE_COUNT 31:0
+#define NV906F_CRC_CHECK (0x0000007c)
+#define NV906F_CRC_CHECK_VALUE 31:0
+#define NV906F_YIELD (0x00000080)
+#define NV906F_YIELD_OP 1:0
+#define NV906F_YIELD_OP_NOP 0x00000000
+
+
+/* GPFIFO entry format */
+#define NV906F_GP_ENTRY__SIZE 8
+#define NV906F_GP_ENTRY0_FETCH 0:0
+#define NV906F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
+#define NV906F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
+#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH 1:1
+#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH_FALSE 0x00000000
+#define NV906F_GP_ENTRY0_NO_CONTEXT_SWITCH_TRUE 0x00000001
+#define NV906F_GP_ENTRY0_GET 31:2
+#define NV906F_GP_ENTRY0_OPERAND 31:0
+#define NV906F_GP_ENTRY1_GET_HI 7:0
+#define NV906F_GP_ENTRY1_PRIV 8:8
+#define NV906F_GP_ENTRY1_PRIV_USER 0x00000000
+#define NV906F_GP_ENTRY1_PRIV_KERNEL 0x00000001
+#define NV906F_GP_ENTRY1_LEVEL 9:9
+#define NV906F_GP_ENTRY1_LEVEL_MAIN 0x00000000
+#define NV906F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
+#define NV906F_GP_ENTRY1_LENGTH 30:10
+#define NV906F_GP_ENTRY1_SYNC 31:31
+#define NV906F_GP_ENTRY1_SYNC_PROCEED 0x00000000
+#define NV906F_GP_ENTRY1_SYNC_WAIT 0x00000001
+#define NV906F_GP_ENTRY1_OPCODE 7:0
+#define NV906F_GP_ENTRY1_OPCODE_NOP 0x00000000
+#define NV906F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
+#define NV906F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
+#define NV906F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
+
+/* dma method formats */
+#define NV906F_DMA_METHOD_ADDRESS_OLD 12:2
+#define NV906F_DMA_METHOD_ADDRESS 11:0
+#define NV906F_DMA_SUBDEVICE_MASK 15:4
+#define NV906F_DMA_METHOD_SUBCHANNEL 15:13
+#define NV906F_DMA_TERT_OP 17:16
+#define NV906F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
+#define NV906F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
+#define NV906F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
+#define NV906F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
+#define NV906F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
+#define NV906F_DMA_METHOD_COUNT_OLD 28:18
+#define NV906F_DMA_METHOD_COUNT 28:16
+#define NV906F_DMA_IMMD_DATA 28:16
+#define NV906F_DMA_SEC_OP 31:29
+#define NV906F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
+#define NV906F_DMA_SEC_OP_INC_METHOD (0x00000001)
+#define NV906F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
+#define NV906F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
+#define NV906F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
+#define NV906F_DMA_SEC_OP_ONE_INC (0x00000005)
+#define NV906F_DMA_SEC_OP_RESERVED6 (0x00000006)
+#define NV906F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
+/* dma incrementing method format */
+#define NV906F_DMA_INCR_ADDRESS 11:0
+#define NV906F_DMA_INCR_SUBCHANNEL 15:13
+#define NV906F_DMA_INCR_COUNT 28:16
+#define NV906F_DMA_INCR_OPCODE 31:29
+#define NV906F_DMA_INCR_OPCODE_VALUE (0x00000001)
+#define NV906F_DMA_INCR_DATA 31:0
+/* dma non-incrementing method format */
+#define NV906F_DMA_NONINCR_ADDRESS 11:0
+#define NV906F_DMA_NONINCR_SUBCHANNEL 15:13
+#define NV906F_DMA_NONINCR_COUNT 28:16
+#define NV906F_DMA_NONINCR_OPCODE 31:29
+#define NV906F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
+#define NV906F_DMA_NONINCR_DATA 31:0
+/* dma increment-once method format */
+#define NV906F_DMA_ONEINCR_ADDRESS 11:0
+#define NV906F_DMA_ONEINCR_SUBCHANNEL 15:13
+#define NV906F_DMA_ONEINCR_COUNT 28:16
+#define NV906F_DMA_ONEINCR_OPCODE 31:29
+#define NV906F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
+#define NV906F_DMA_ONEINCR_DATA 31:0
+/* dma no-operation format */
+#define NV906F_DMA_NOP (0x00000000)
+/* dma immediate-data format */
+#define NV906F_DMA_IMMD_ADDRESS 11:0
+#define NV906F_DMA_IMMD_SUBCHANNEL 15:13
+#define NV906F_DMA_IMMD_DATA 28:16
+#define NV906F_DMA_IMMD_OPCODE 31:29
+#define NV906F_DMA_IMMD_OPCODE_VALUE (0x00000004)
+/* dma set sub-device mask format */
+#define NV906F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NV906F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
+#define NV906F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
+/* dma store sub-device mask format */
+#define NV906F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
+#define NV906F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
+#define NV906F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
+/* dma use sub-device mask format */
+#define NV906F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
+#define NV906F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
+/* dma end-segment format */
+#define NV906F_DMA_ENDSEG_OPCODE 31:29
+#define NV906F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
+/* dma legacy incrementing/non-incrementing formats */
+#define NV906F_DMA_ADDRESS 12:2
+#define NV906F_DMA_SUBCH 15:13
+#define NV906F_DMA_OPCODE3 17:16
+#define NV906F_DMA_OPCODE3_NONE (0x00000000)
+#define NV906F_DMA_COUNT 28:18
+#define NV906F_DMA_OPCODE 31:29
+#define NV906F_DMA_OPCODE_METHOD (0x00000000)
+#define NV906F_DMA_OPCODE_NONINC_METHOD (0x00000002)
+#define NV906F_DMA_DATA 31:0
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _cl906f_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _clA06f_h_
+#define _clA06f_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class KEPLER_CHANNEL_GPFIFO */
+/*
+ * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
+ * chapter "User Control Registers". It is documented as device NV_UDMA.
+ * The GPFIFO format itself is also documented in dev_pbdma.ref,
+ * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
+ * chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
+ *
+ */
+#define KEPLER_CHANNEL_GPFIFO_A (0x0000A06F)
+
+
+/* pio method data structure */
+typedef volatile struct _cla06f_tag0 {
+ NvV32 Reserved00[0x7c0];
+} NvA06FTypedef, KEPLER_ChannelGPFifo;
+#define NVA06F_TYPEDEF KEPLER_CHANNELChannelGPFifo
+/* dma flow control data structure */
+typedef volatile struct _cla06f_tag1 {
+ NvU32 Ignored00[0x010]; /* 0000-0043*/
+ NvU32 Put; /* put offset, read/write 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 PutHi; /* high order put offset bits 004c-004f*/
+ NvU32 Ignored01[0x002]; /* 0050-0057*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
+ NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
+ NvU32 GetHi; /* high order get offset bits 0060-0063*/
+ NvU32 Ignored02[0x007]; /* 0064-007f*/
+ NvU32 Ignored03; /* used to be engine yield 0080-0083*/
+ NvU32 Ignored04[0x001]; /* 0084-0087*/
+ NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
+ NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
+ NvU32 Ignored05[0x5c];
+} NvA06FControl, KeplerAControlGPFifo;
+/* fields and values */
+#define NVA06F_NUMBER_OF_SUBCHANNELS (8)
+#define NVA06F_SET_OBJECT (0x00000000)
+#define NVA06F_SET_OBJECT_NVCLASS 15:0
+#define NVA06F_SET_OBJECT_ENGINE 20:16
+#define NVA06F_SET_OBJECT_ENGINE_SW 0x0000001f
+#define NVA06F_ILLEGAL (0x00000004)
+#define NVA06F_ILLEGAL_HANDLE 31:0
+#define NVA06F_NOP (0x00000008)
+#define NVA06F_NOP_HANDLE 31:0
+#define NVA06F_SEMAPHOREA (0x00000010)
+#define NVA06F_SEMAPHOREA_OFFSET_UPPER 7:0
+#define NVA06F_SEMAPHOREB (0x00000014)
+#define NVA06F_SEMAPHOREB_OFFSET_LOWER 31:2
+#define NVA06F_SEMAPHOREC (0x00000018)
+#define NVA06F_SEMAPHOREC_PAYLOAD 31:0
+#define NVA06F_SEMAPHORED (0x0000001C)
+#define NVA06F_SEMAPHORED_OPERATION 3:0
+#define NVA06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
+#define NVA06F_SEMAPHORED_OPERATION_RELEASE 0x00000002
+#define NVA06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
+#define NVA06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
+#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH 12:12
+#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
+#define NVA06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
+#define NVA06F_SEMAPHORED_RELEASE_WFI 20:20
+#define NVA06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
+#define NVA06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
+#define NVA06F_SEMAPHORED_RELEASE_SIZE 24:24
+#define NVA06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
+#define NVA06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
+#define NVA06F_NON_STALL_INTERRUPT (0x00000020)
+#define NVA06F_NON_STALL_INTERRUPT_HANDLE 31:0
+#define NVA06F_FB_FLUSH (0x00000024)
+#define NVA06F_FB_FLUSH_HANDLE 31:0
+#define NVA06F_MEM_OP_A (0x00000028)
+#define NVA06F_MEM_OP_A_OPERAND_LOW 31:2
+#define NVA06F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2
+#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30
+#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000
+#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002
+#define NVA06F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003
+#define NVA06F_MEM_OP_B (0x0000002c)
+#define NVA06F_MEM_OP_B_OPERAND_HIGH 7:0
+#define NVA06F_MEM_OP_B_OPERATION 31:27
+#define NVA06F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005
+#define NVA06F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006
+#define NVA06F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009
+#define NVA06F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
+#define NVA06F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
+#define NVA06F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
+#define NVA06F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010
+#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0
+#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000
+#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001
+#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1
+#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000
+#define NVA06F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001
+#define NVA06F_SET_REFERENCE (0x00000050)
+#define NVA06F_SET_REFERENCE_COUNT 31:0
+#define NVA06F_CRC_CHECK (0x0000007c)
+#define NVA06F_CRC_CHECK_VALUE 31:0
+#define NVA06F_YIELD (0x00000080)
+#define NVA06F_YIELD_OP 1:0
+#define NVA06F_YIELD_OP_NOP 0x00000000
+
+
+/* GPFIFO entry format */
+#define NVA06F_GP_ENTRY__SIZE 8
+#define NVA06F_GP_ENTRY0_FETCH 0:0
+#define NVA06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
+#define NVA06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
+#define NVA06F_GP_ENTRY0_GET 31:2
+#define NVA06F_GP_ENTRY0_OPERAND 31:0
+#define NVA06F_GP_ENTRY1_GET_HI 7:0
+#define NVA06F_GP_ENTRY1_PRIV 8:8
+#define NVA06F_GP_ENTRY1_PRIV_USER 0x00000000
+#define NVA06F_GP_ENTRY1_PRIV_KERNEL 0x00000001
+#define NVA06F_GP_ENTRY1_LEVEL 9:9
+#define NVA06F_GP_ENTRY1_LEVEL_MAIN 0x00000000
+#define NVA06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
+#define NVA06F_GP_ENTRY1_LENGTH 30:10
+#define NVA06F_GP_ENTRY1_SYNC 31:31
+#define NVA06F_GP_ENTRY1_SYNC_PROCEED 0x00000000
+#define NVA06F_GP_ENTRY1_SYNC_WAIT 0x00000001
+#define NVA06F_GP_ENTRY1_OPCODE 7:0
+#define NVA06F_GP_ENTRY1_OPCODE_NOP 0x00000000
+#define NVA06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
+#define NVA06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
+#define NVA06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
+
+/* dma method formats */
+#define NVA06F_DMA_METHOD_ADDRESS_OLD 12:2
+#define NVA06F_DMA_METHOD_ADDRESS 11:0
+#define NVA06F_DMA_SUBDEVICE_MASK 15:4
+#define NVA06F_DMA_METHOD_SUBCHANNEL 15:13
+#define NVA06F_DMA_TERT_OP 17:16
+#define NVA06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
+#define NVA06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
+#define NVA06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
+#define NVA06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
+#define NVA06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
+#define NVA06F_DMA_METHOD_COUNT_OLD 28:18
+#define NVA06F_DMA_METHOD_COUNT 28:16
+#define NVA06F_DMA_IMMD_DATA 28:16
+#define NVA06F_DMA_SEC_OP 31:29
+#define NVA06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
+#define NVA06F_DMA_SEC_OP_INC_METHOD (0x00000001)
+#define NVA06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
+#define NVA06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
+#define NVA06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
+#define NVA06F_DMA_SEC_OP_ONE_INC (0x00000005)
+#define NVA06F_DMA_SEC_OP_RESERVED6 (0x00000006)
+#define NVA06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
+/* dma incrementing method format */
+#define NVA06F_DMA_INCR_ADDRESS 11:0
+#define NVA06F_DMA_INCR_SUBCHANNEL 15:13
+#define NVA06F_DMA_INCR_COUNT 28:16
+#define NVA06F_DMA_INCR_OPCODE 31:29
+#define NVA06F_DMA_INCR_OPCODE_VALUE (0x00000001)
+#define NVA06F_DMA_INCR_DATA 31:0
+/* dma non-incrementing method format */
+#define NVA06F_DMA_NONINCR_ADDRESS 11:0
+#define NVA06F_DMA_NONINCR_SUBCHANNEL 15:13
+#define NVA06F_DMA_NONINCR_COUNT 28:16
+#define NVA06F_DMA_NONINCR_OPCODE 31:29
+#define NVA06F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
+#define NVA06F_DMA_NONINCR_DATA 31:0
+/* dma increment-once method format */
+#define NVA06F_DMA_ONEINCR_ADDRESS 11:0
+#define NVA06F_DMA_ONEINCR_SUBCHANNEL 15:13
+#define NVA06F_DMA_ONEINCR_COUNT 28:16
+#define NVA06F_DMA_ONEINCR_OPCODE 31:29
+#define NVA06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
+#define NVA06F_DMA_ONEINCR_DATA 31:0
+/* dma no-operation format */
+#define NVA06F_DMA_NOP (0x00000000)
+/* dma immediate-data format */
+#define NVA06F_DMA_IMMD_ADDRESS 11:0
+#define NVA06F_DMA_IMMD_SUBCHANNEL 15:13
+#define NVA06F_DMA_IMMD_DATA 28:16
+#define NVA06F_DMA_IMMD_OPCODE 31:29
+#define NVA06F_DMA_IMMD_OPCODE_VALUE (0x00000004)
+/* dma set sub-device mask format */
+#define NVA06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NVA06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
+#define NVA06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
+/* dma store sub-device mask format */
+#define NVA06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
+#define NVA06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVA06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
+/* dma use sub-device mask format */
+#define NVA06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVA06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
+/* dma end-segment format */
+#define NVA06F_DMA_ENDSEG_OPCODE 31:29
+#define NVA06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
+/* dma legacy incrementing/non-incrementing formats */
+#define NVA06F_DMA_ADDRESS 12:2
+#define NVA06F_DMA_SUBCH 15:13
+#define NVA06F_DMA_OPCODE3 17:16
+#define NVA06F_DMA_OPCODE3_NONE (0x00000000)
+#define NVA06F_DMA_COUNT 28:18
+#define NVA06F_DMA_OPCODE 31:29
+#define NVA06F_DMA_OPCODE_METHOD (0x00000000)
+#define NVA06F_DMA_OPCODE_NONINC_METHOD (0x00000002)
+#define NVA06F_DMA_DATA 31:0
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _clA06F_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cla16f_h_
+#define _cla16f_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class KEPLER_CHANNEL_GPFIFO */
+/*
+ * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
+ * chapter "User Control Registers". It is documented as device NV_UDMA.
+ * The GPFIFO format itself is also documented in dev_pbdma.ref,
+ * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
+ * chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
+ *
+ */
+#define KEPLER_CHANNEL_GPFIFO_B (0x0000A16F)
+
+/* pio method data structure */
+typedef volatile struct _cla16f_tag0 {
+ NvV32 Reserved00[0x7c0];
+} NvA16FTypedef, KEPLER_ChannelGPFifoB;
+#define NVA16F_TYPEDEF KEPLER_CHANNELChannelGPFifo
+/* dma flow control data structure */
+typedef volatile struct _cla16f_tag1 {
+ NvU32 Ignored00[0x010]; /* 0000-003f*/
+ NvU32 Put; /* put offset, read/write 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 PutHi; /* high order put offset bits 004c-004f*/
+ NvU32 Ignored01[0x002]; /* 0050-0057*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
+ NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
+ NvU32 GetHi; /* high order get offset bits 0060-0063*/
+ NvU32 Ignored02[0x007]; /* 0064-007f*/
+ NvU32 Ignored03; /* used to be engine yield 0080-0083*/
+ NvU32 Ignored04[0x001]; /* 0084-0087*/
+ NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
+ NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
+ NvU32 Ignored05[0x5c];
+} NvA16FControl, KeplerBControlGPFifo;
+/* fields and values */
+#define NVA16F_NUMBER_OF_SUBCHANNELS (8)
+#define NVA16F_SET_OBJECT (0x00000000)
+#define NVA16F_SET_OBJECT_NVCLASS 15:0
+#define NVA16F_SET_OBJECT_ENGINE 20:16
+#define NVA16F_SET_OBJECT_ENGINE_SW 0x0000001f
+#define NVA16F_ILLEGAL (0x00000004)
+#define NVA16F_ILLEGAL_HANDLE 31:0
+#define NVA16F_NOP (0x00000008)
+#define NVA16F_NOP_HANDLE 31:0
+#define NVA16F_SEMAPHOREA (0x00000010)
+#define NVA16F_SEMAPHOREA_OFFSET_UPPER 7:0
+#define NVA16F_SEMAPHOREB (0x00000014)
+#define NVA16F_SEMAPHOREB_OFFSET_LOWER 31:2
+#define NVA16F_SEMAPHOREC (0x00000018)
+#define NVA16F_SEMAPHOREC_PAYLOAD 31:0
+#define NVA16F_SEMAPHORED (0x0000001C)
+#define NVA16F_SEMAPHORED_OPERATION 4:0
+#define NVA16F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
+#define NVA16F_SEMAPHORED_OPERATION_RELEASE 0x00000002
+#define NVA16F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
+#define NVA16F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
+#define NVA16F_SEMAPHORED_OPERATION_REDUCTION 0x00000010
+#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH 12:12
+#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
+#define NVA16F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
+#define NVA16F_SEMAPHORED_RELEASE_WFI 20:20
+#define NVA16F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
+#define NVA16F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
+#define NVA16F_SEMAPHORED_RELEASE_SIZE 24:24
+#define NVA16F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
+#define NVA16F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
+#define NVA16F_SEMAPHORED_REDUCTION 30:27
+#define NVA16F_SEMAPHORED_REDUCTION_MIN 0x00000000
+#define NVA16F_SEMAPHORED_REDUCTION_MAX 0x00000001
+#define NVA16F_SEMAPHORED_REDUCTION_XOR 0x00000002
+#define NVA16F_SEMAPHORED_REDUCTION_AND 0x00000003
+#define NVA16F_SEMAPHORED_REDUCTION_OR 0x00000004
+#define NVA16F_SEMAPHORED_REDUCTION_ADD 0x00000005
+#define NVA16F_SEMAPHORED_REDUCTION_INC 0x00000006
+#define NVA16F_SEMAPHORED_REDUCTION_DEC 0x00000007
+#define NVA16F_SEMAPHORED_FORMAT 31:31
+#define NVA16F_SEMAPHORED_FORMAT_SIGNED 0x00000000
+#define NVA16F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001
+#define NVA16F_NON_STALL_INTERRUPT (0x00000020)
+#define NVA16F_NON_STALL_INTERRUPT_HANDLE 31:0
+#define NVA16F_FB_FLUSH (0x00000024)
+#define NVA16F_FB_FLUSH_HANDLE 31:0
+#define NVA16F_MEM_OP_A (0x00000028)
+#define NVA16F_MEM_OP_A_OPERAND_LOW 31:2
+#define NVA16F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2
+#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30
+#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000
+#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002
+#define NVA16F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003
+#define NVA16F_MEM_OP_B (0x0000002c)
+#define NVA16F_MEM_OP_B_OPERAND_HIGH 7:0
+#define NVA16F_MEM_OP_B_OPERATION 31:27
+#define NVA16F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005
+#define NVA16F_MEM_OP_B_OPERATION_SOFT_FLUSH 0x00000006
+#define NVA16F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009
+#define NVA16F_MEM_OP_B_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
+#define NVA16F_MEM_OP_B_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
+#define NVA16F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
+#define NVA16F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010
+#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0
+#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000
+#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001
+#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1
+#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000
+#define NVA16F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001
+#define NVA16F_SET_REFERENCE (0x00000050)
+#define NVA16F_SET_REFERENCE_COUNT 31:0
+#define NVA16F_WFI (0x00000078)
+#define NVA16F_WFI_HANDLE 31:0
+#define NVA16F_CRC_CHECK (0x0000007c)
+#define NVA16F_CRC_CHECK_VALUE 31:0
+#define NVA16F_YIELD (0x00000080)
+#define NVA16F_YIELD_OP 1:0
+#define NVA16F_YIELD_OP_NOP 0x00000000
+
+
+/* GPFIFO entry format */
+#define NVA16F_GP_ENTRY__SIZE 8
+#define NVA16F_GP_ENTRY0_FETCH 0:0
+#define NVA16F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
+#define NVA16F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
+#define NVA16F_GP_ENTRY0_GET 31:2
+#define NVA16F_GP_ENTRY0_OPERAND 31:0
+#define NVA16F_GP_ENTRY1_GET_HI 7:0
+#define NVA16F_GP_ENTRY1_PRIV 8:8
+#define NVA16F_GP_ENTRY1_PRIV_USER 0x00000000
+#define NVA16F_GP_ENTRY1_PRIV_KERNEL 0x00000001
+#define NVA16F_GP_ENTRY1_LEVEL 9:9
+#define NVA16F_GP_ENTRY1_LEVEL_MAIN 0x00000000
+#define NVA16F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
+#define NVA16F_GP_ENTRY1_LENGTH 30:10
+#define NVA16F_GP_ENTRY1_SYNC 31:31
+#define NVA16F_GP_ENTRY1_SYNC_PROCEED 0x00000000
+#define NVA16F_GP_ENTRY1_SYNC_WAIT 0x00000001
+#define NVA16F_GP_ENTRY1_OPCODE 7:0
+#define NVA16F_GP_ENTRY1_OPCODE_NOP 0x00000000
+#define NVA16F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
+#define NVA16F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
+#define NVA16F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
+
+/* dma method formats */
+#define NVA16F_DMA_METHOD_ADDRESS_OLD 12:2
+#define NVA16F_DMA_METHOD_ADDRESS 11:0
+#define NVA16F_DMA_SUBDEVICE_MASK 15:4
+#define NVA16F_DMA_METHOD_SUBCHANNEL 15:13
+#define NVA16F_DMA_TERT_OP 17:16
+#define NVA16F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
+#define NVA16F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
+#define NVA16F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
+#define NVA16F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
+#define NVA16F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
+#define NVA16F_DMA_METHOD_COUNT_OLD 28:18
+#define NVA16F_DMA_METHOD_COUNT 28:16
+#define NVA16F_DMA_IMMD_DATA 28:16
+#define NVA16F_DMA_SEC_OP 31:29
+#define NVA16F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
+#define NVA16F_DMA_SEC_OP_INC_METHOD (0x00000001)
+#define NVA16F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
+#define NVA16F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
+#define NVA16F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
+#define NVA16F_DMA_SEC_OP_ONE_INC (0x00000005)
+#define NVA16F_DMA_SEC_OP_RESERVED6 (0x00000006)
+#define NVA16F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
+/* dma incrementing method format */
+#define NVA16F_DMA_INCR_ADDRESS 11:0
+#define NVA16F_DMA_INCR_SUBCHANNEL 15:13
+#define NVA16F_DMA_INCR_COUNT 28:16
+#define NVA16F_DMA_INCR_OPCODE 31:29
+#define NVA16F_DMA_INCR_OPCODE_VALUE (0x00000001)
+#define NVA16F_DMA_INCR_DATA 31:0
+/* dma non-incrementing method format */
+#define NVA16F_DMA_NONINCR_ADDRESS 11:0
+#define NVA16F_DMA_NONINCR_SUBCHANNEL 15:13
+#define NVA16F_DMA_NONINCR_COUNT 28:16
+#define NVA16F_DMA_NONINCR_OPCODE 31:29
+#define NVA16F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
+#define NVA16F_DMA_NONINCR_DATA 31:0
+/* dma increment-once method format */
+#define NVA16F_DMA_ONEINCR_ADDRESS 11:0
+#define NVA16F_DMA_ONEINCR_SUBCHANNEL 15:13
+#define NVA16F_DMA_ONEINCR_COUNT 28:16
+#define NVA16F_DMA_ONEINCR_OPCODE 31:29
+#define NVA16F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
+#define NVA16F_DMA_ONEINCR_DATA 31:0
+/* dma no-operation format */
+#define NVA16F_DMA_NOP (0x00000000)
+/* dma immediate-data format */
+#define NVA16F_DMA_IMMD_ADDRESS 11:0
+#define NVA16F_DMA_IMMD_SUBCHANNEL 15:13
+#define NVA16F_DMA_IMMD_DATA 28:16
+#define NVA16F_DMA_IMMD_OPCODE 31:29
+#define NVA16F_DMA_IMMD_OPCODE_VALUE (0x00000004)
+/* dma set sub-device mask format */
+#define NVA16F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NVA16F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
+#define NVA16F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
+/* dma store sub-device mask format */
+#define NVA16F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
+#define NVA16F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVA16F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
+/* dma use sub-device mask format */
+#define NVA16F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVA16F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
+/* dma end-segment format */
+#define NVA16F_DMA_ENDSEG_OPCODE 31:29
+#define NVA16F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
+/* dma legacy incrementing/non-incrementing formats */
+#define NVA16F_DMA_ADDRESS 12:2
+#define NVA16F_DMA_SUBCH 15:13
+#define NVA16F_DMA_OPCODE3 17:16
+#define NVA16F_DMA_OPCODE3_NONE (0x00000000)
+#define NVA16F_DMA_COUNT 28:18
+#define NVA16F_DMA_OPCODE 31:29
+#define NVA16F_DMA_OPCODE_METHOD (0x00000000)
+#define NVA16F_DMA_OPCODE_NONINC_METHOD (0x00000002)
+#define NVA16F_DMA_DATA 31:0
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _cla16F_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cla26f_h_
+#define _cla26f_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class KEPLER_CHANNEL_GPFIFO */
+/*
+ * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
+ * chapter "User Control Registers". It is documented as device NV_UDMA.
+ * The GPFIFO format itself is also documented in dev_pbdma.ref,
+ * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
+ * chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
+ *
+ */
+#define KEPLER_CHANNEL_GPFIFO_C (0x0000A26F)
+
+/* pio method data structure */
+typedef volatile struct _cla26f_tag0 {
+ NvV32 Reserved00[0x7c0];
+} NvA26FTypedef, KEPLER_ChannelGPFifoC;
+#define NVA26F_TYPEDEF KEPLER_CHANNELChannelGPFifo
+/* dma flow control data structure */
+typedef volatile struct _cla26f_tag1 {
+ NvU32 Ignored00[0x010]; /* 0000-003f*/
+ NvU32 Put; /* put offset, read/write 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 PutHi; /* high order put offset bits 004c-004f*/
+ NvU32 Ignored01[0x002]; /* 0050-0057*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
+ NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
+ NvU32 GetHi; /* high order get offset bits 0060-0063*/
+ NvU32 Ignored02[0x007]; /* 0064-007f*/
+ NvU32 Ignored03; /* used to be engine yield 0080-0083*/
+ NvU32 Ignored04[0x001]; /* 0084-0087*/
+ NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
+ NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
+ NvU32 Ignored05[0x5c];
+} NvA26FControl, KeplerCControlGPFifo;
+/* fields and values */
+#define NVA26F_NUMBER_OF_SUBCHANNELS (8)
+#define NVA26F_SET_OBJECT (0x00000000)
+#define NVA26F_SET_OBJECT_NVCLASS 15:0
+#define NVA26F_SET_OBJECT_ENGINE 20:16
+#define NVA26F_SET_OBJECT_ENGINE_SW 0x0000001f
+#define NVA26F_ILLEGAL (0x00000004)
+#define NVA26F_ILLEGAL_HANDLE 31:0
+#define NVA26F_NOP (0x00000008)
+#define NVA26F_NOP_HANDLE 31:0
+#define NVA26F_SEMAPHOREA (0x00000010)
+#define NVA26F_SEMAPHOREA_OFFSET_UPPER 7:0
+#define NVA26F_SEMAPHOREB (0x00000014)
+#define NVA26F_SEMAPHOREB_OFFSET_LOWER 31:2
+#define NVA26F_SEMAPHOREC (0x00000018)
+#define NVA26F_SEMAPHOREC_PAYLOAD 31:0
+#define NVA26F_SEMAPHORED (0x0000001C)
+#define NVA26F_SEMAPHORED_OPERATION 3:0
+#define NVA26F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
+#define NVA26F_SEMAPHORED_OPERATION_RELEASE 0x00000002
+#define NVA26F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
+#define NVA26F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
+#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH 12:12
+#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
+#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
+#define NVA26F_SEMAPHORED_RELEASE_WFI 20:20
+#define NVA26F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
+#define NVA26F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
+#define NVA26F_SEMAPHORED_RELEASE_SIZE 24:24
+#define NVA26F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
+#define NVA26F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
+#define NVA26F_NON_STALL_INTERRUPT (0x00000020)
+#define NVA26F_NON_STALL_INTERRUPT_HANDLE 31:0
+#define NVA26F_FB_FLUSH (0x00000024)
+#define NVA26F_FB_FLUSH_HANDLE 31:0
+#define NVA26F_MEM_OP_A (0x00000028)
+#define NVA26F_MEM_OP_A_OPERAND_LOW 31:2
+#define NVA26F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2
+#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30
+#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000
+#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002
+#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003
+#define NVA26F_MEM_OP_B (0x0000002c)
+#define NVA26F_MEM_OP_B_OPERAND_HIGH 7:0
+#define NVA26F_MEM_OP_B_OPERATION 31:27
+#define NVA26F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005
+#define NVA26F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009
+#define NVA26F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e
+#define NVA26F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
+#define NVA26F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010
+#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0
+#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000
+#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001
+#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1
+#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000
+#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001
+#define NVA26F_SET_REFERENCE (0x00000050)
+#define NVA26F_SET_REFERENCE_COUNT 31:0
+#define NVA26F_SYNCPOINTA (0x00000070)
+#define NVA26F_SYNCPOINTA_PAYLOAD 31:0
+#define NVA26F_SYNCPOINTB (0x00000074)
+#define NVA26F_SYNCPOINTB_OPERATION 1:0
+#define NVA26F_SYNCPOINTB_OPERATION_WAIT 0x00000000
+#define NVA26F_SYNCPOINTB_OPERATION_INCR 0x00000001
+#define NVA26F_SYNCPOINTB_OPERATION_BASE_ADD 0x00000002
+#define NVA26F_SYNCPOINTB_OPERATION_BASE_WRITE 0x00000003
+#define NVA26F_SYNCPOINTB_WAIT_SWITCH 4:4
+#define NVA26F_SYNCPOINTB_WAIT_SWITCH_DIS 0x00000000
+#define NVA26F_SYNCPOINTB_WAIT_SWITCH_EN 0x00000001
+#define NVA26F_SYNCPOINTB_BASE 5:5
+#define NVA26F_SYNCPOINTB_BASE_DIS 0x00000000
+#define NVA26F_SYNCPOINTB_BASE_EN 0x00000001
+#define NVA26F_SYNCPOINTB_SYNCPT_INDEX 15:8
+#define NVA26F_SYNCPOINTB_BASE_INDEX 25:20
+#define NVA26F_WFI (0x00000078)
+#define NVA26F_WFI_HANDLE 31:0
+#define NVA26F_CRC_CHECK (0x0000007c)
+#define NVA26F_CRC_CHECK_VALUE 31:0
+#define NVA26F_YIELD (0x00000080)
+#define NVA26F_YIELD_OP 1:0
+#define NVA26F_YIELD_OP_NOP 0x00000000
+
+
+/* GPFIFO entry format */
+#define NVA26F_GP_ENTRY__SIZE 8
+#define NVA26F_GP_ENTRY0_FETCH 0:0
+#define NVA26F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
+#define NVA26F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
+#define NVA26F_GP_ENTRY0_GET 31:2
+#define NVA26F_GP_ENTRY0_OPERAND 31:0
+#define NVA26F_GP_ENTRY1_GET_HI 7:0
+#define NVA26F_GP_ENTRY1_PRIV 8:8
+#define NVA26F_GP_ENTRY1_PRIV_USER 0x00000000
+#define NVA26F_GP_ENTRY1_PRIV_KERNEL 0x00000001
+#define NVA26F_GP_ENTRY1_LEVEL 9:9
+#define NVA26F_GP_ENTRY1_LEVEL_MAIN 0x00000000
+#define NVA26F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
+#define NVA26F_GP_ENTRY1_LENGTH 30:10
+#define NVA26F_GP_ENTRY1_SYNC 31:31
+#define NVA26F_GP_ENTRY1_SYNC_PROCEED 0x00000000
+#define NVA26F_GP_ENTRY1_SYNC_WAIT 0x00000001
+#define NVA26F_GP_ENTRY1_OPCODE 7:0
+#define NVA26F_GP_ENTRY1_OPCODE_NOP 0x00000000
+#define NVA26F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
+#define NVA26F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
+#define NVA26F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
+
+/* dma method formats */
+#define NVA26F_DMA_METHOD_ADDRESS_OLD 12:2
+#define NVA26F_DMA_METHOD_ADDRESS 11:0
+#define NVA26F_DMA_SUBDEVICE_MASK 15:4
+#define NVA26F_DMA_METHOD_SUBCHANNEL 15:13
+#define NVA26F_DMA_TERT_OP 17:16
+#define NVA26F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
+#define NVA26F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
+#define NVA26F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
+#define NVA26F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
+#define NVA26F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
+#define NVA26F_DMA_METHOD_COUNT_OLD 28:18
+#define NVA26F_DMA_METHOD_COUNT 28:16
+#define NVA26F_DMA_IMMD_DATA 28:16
+#define NVA26F_DMA_SEC_OP 31:29
+#define NVA26F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
+#define NVA26F_DMA_SEC_OP_INC_METHOD (0x00000001)
+#define NVA26F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
+#define NVA26F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
+#define NVA26F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
+#define NVA26F_DMA_SEC_OP_ONE_INC (0x00000005)
+#define NVA26F_DMA_SEC_OP_RESERVED6 (0x00000006)
+#define NVA26F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
+/* dma incrementing method format */
+#define NVA26F_DMA_INCR_ADDRESS 11:0
+#define NVA26F_DMA_INCR_SUBCHANNEL 15:13
+#define NVA26F_DMA_INCR_COUNT 28:16
+#define NVA26F_DMA_INCR_OPCODE 31:29
+#define NVA26F_DMA_INCR_OPCODE_VALUE (0x00000001)
+#define NVA26F_DMA_INCR_DATA 31:0
+/* dma non-incrementing method format */
+#define NVA26F_DMA_NONINCR_ADDRESS 11:0
+#define NVA26F_DMA_NONINCR_SUBCHANNEL 15:13
+#define NVA26F_DMA_NONINCR_COUNT 28:16
+#define NVA26F_DMA_NONINCR_OPCODE 31:29
+#define NVA26F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
+#define NVA26F_DMA_NONINCR_DATA 31:0
+/* dma increment-once method format */
+#define NVA26F_DMA_ONEINCR_ADDRESS 11:0
+#define NVA26F_DMA_ONEINCR_SUBCHANNEL 15:13
+#define NVA26F_DMA_ONEINCR_COUNT 28:16
+#define NVA26F_DMA_ONEINCR_OPCODE 31:29
+#define NVA26F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
+#define NVA26F_DMA_ONEINCR_DATA 31:0
+/* dma no-operation format */
+#define NVA26F_DMA_NOP (0x00000000)
+/* dma immediate-data format */
+#define NVA26F_DMA_IMMD_ADDRESS 11:0
+#define NVA26F_DMA_IMMD_SUBCHANNEL 15:13
+#define NVA26F_DMA_IMMD_DATA 28:16
+#define NVA26F_DMA_IMMD_OPCODE 31:29
+#define NVA26F_DMA_IMMD_OPCODE_VALUE (0x00000004)
+/* dma set sub-device mask format */
+#define NVA26F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NVA26F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
+#define NVA26F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
+/* dma store sub-device mask format */
+#define NVA26F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
+#define NVA26F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVA26F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
+/* dma use sub-device mask format */
+#define NVA26F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVA26F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
+/* dma end-segment format */
+#define NVA26F_DMA_ENDSEG_OPCODE 31:29
+#define NVA26F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
+/* dma legacy incrementing/non-incrementing formats */
+#define NVA26F_DMA_ADDRESS 12:2
+#define NVA26F_DMA_SUBCH 15:13
+#define NVA26F_DMA_OPCODE3 17:16
+#define NVA26F_DMA_OPCODE3_NONE (0x00000000)
+#define NVA26F_DMA_COUNT 28:18
+#define NVA26F_DMA_OPCODE 31:29
+#define NVA26F_DMA_OPCODE_METHOD (0x00000000)
+#define NVA26F_DMA_OPCODE_NONINC_METHOD (0x00000002)
+#define NVA26F_DMA_DATA 31:0
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _cla26f_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _clb06f_h_
+#define _clb06f_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class MAXWELL_CHANNEL_GPFIFO */
+/*
+ * Documentation for MAXWELL_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
+ * chapter "User Control Registers". It is documented as device NV_UDMA.
+ * The GPFIFO format itself is also documented in dev_pbdma.ref,
+ * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
+ * chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
+ *
+ */
+#define MAXWELL_CHANNEL_GPFIFO_A (0x0000B06F)
+
+#define NVB06F_TYPEDEF MAXWELL_CHANNELChannelGPFifoA
+
+/* dma flow control data structure */
+typedef volatile struct _clb06f_tag0 {
+ NvU32 Ignored00[0x010]; /* 0000-003f*/
+ NvU32 Put; /* put offset, read/write 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 PutHi; /* high order put offset bits 004c-004f*/
+ NvU32 Ignored01[0x002]; /* 0050-0057*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
+ NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
+ NvU32 GetHi; /* high order get offset bits 0060-0063*/
+ NvU32 Ignored02[0x007]; /* 0064-007f*/
+ NvU32 Ignored03; /* used to be engine yield 0080-0083*/
+ NvU32 Ignored04[0x001]; /* 0084-0087*/
+ NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
+ NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
+ NvU32 Ignored05[0x5c];
+} Nvb06FControl, MaxwellAControlGPFifo;
+
+/* fields and values */
+#define NVB06F_NUMBER_OF_SUBCHANNELS (8)
+#define NVB06F_SET_OBJECT (0x00000000)
+#define NVB06F_SET_OBJECT_NVCLASS 15:0
+#define NVB06F_SET_OBJECT_ENGINE 20:16
+#define NVB06F_SET_OBJECT_ENGINE_SW 0x0000001f
+#define NVB06F_ILLEGAL (0x00000004)
+#define NVB06F_ILLEGAL_HANDLE 31:0
+#define NVB06F_NOP (0x00000008)
+#define NVB06F_NOP_HANDLE 31:0
+#define NVB06F_SEMAPHOREA (0x00000010)
+#define NVB06F_SEMAPHOREA_OFFSET_UPPER 7:0
+#define NVB06F_SEMAPHOREB (0x00000014)
+#define NVB06F_SEMAPHOREB_OFFSET_LOWER 31:2
+#define NVB06F_SEMAPHOREC (0x00000018)
+#define NVB06F_SEMAPHOREC_PAYLOAD 31:0
+#define NVB06F_SEMAPHORED (0x0000001C)
+#define NVB06F_SEMAPHORED_OPERATION 4:0
+#define NVB06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
+#define NVB06F_SEMAPHORED_OPERATION_RELEASE 0x00000002
+#define NVB06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
+#define NVB06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
+#define NVB06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010
+#define NVB06F_SEMAPHORED_ACQUIRE_SWITCH 12:12
+#define NVB06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
+#define NVB06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
+#define NVB06F_SEMAPHORED_RELEASE_WFI 20:20
+#define NVB06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
+#define NVB06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
+#define NVB06F_SEMAPHORED_RELEASE_SIZE 24:24
+#define NVB06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
+#define NVB06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
+#define NVB06F_SEMAPHORED_REDUCTION 30:27
+#define NVB06F_SEMAPHORED_REDUCTION_MIN 0x00000000
+#define NVB06F_SEMAPHORED_REDUCTION_MAX 0x00000001
+#define NVB06F_SEMAPHORED_REDUCTION_XOR 0x00000002
+#define NVB06F_SEMAPHORED_REDUCTION_AND 0x00000003
+#define NVB06F_SEMAPHORED_REDUCTION_OR 0x00000004
+#define NVB06F_SEMAPHORED_REDUCTION_ADD 0x00000005
+#define NVB06F_SEMAPHORED_REDUCTION_INC 0x00000006
+#define NVB06F_SEMAPHORED_REDUCTION_DEC 0x00000007
+#define NVB06F_SEMAPHORED_FORMAT 31:31
+#define NVB06F_SEMAPHORED_FORMAT_SIGNED 0x00000000
+#define NVB06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001
+#define NVB06F_NON_STALL_INTERRUPT (0x00000020)
+#define NVB06F_NON_STALL_INTERRUPT_HANDLE 31:0
+#define NVB06F_FB_FLUSH (0x00000024)
+#define NVB06F_FB_FLUSH_HANDLE 31:0
+// NOTE - MEM_OP_A and MEM_OP_B have been removed for gm20x to make room for
+// possible future MEM_OP features. MEM_OP_C/D have identical functionality
+// to the previous MEM_OP_A/B methods.
+#define NVB06F_MEM_OP_C (0x00000030)
+#define NVB06F_MEM_OP_C_OPERAND_LOW 31:2
+#define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0
+#define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000
+#define NVB06F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001
+#define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1
+#define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000
+#define NVB06F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001
+#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET 11:10
+#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000
+#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002
+#define NVB06F_MEM_OP_C_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003
+#define NVB06F_MEM_OP_C_TLB_INVALIDATE_ADDR_LO 31:12
+#define NVB06F_MEM_OP_D (0x00000034)
+#define NVB06F_MEM_OP_D_OPERAND_HIGH 7:0
+#define NVB06F_MEM_OP_D_OPERATION 31:27
+#define NVB06F_MEM_OP_D_OPERATION_MEMBAR 0x00000005
+#define NVB06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009
+#define NVB06F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
+#define NVB06F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
+#define NVB06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
+#define NVB06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010
+#define NVB06F_MEM_OP_D_TLB_INVALIDATE_ADDR_HI 7:0
+#define NVB06F_SET_REFERENCE (0x00000050)
+#define NVB06F_SET_REFERENCE_COUNT 31:0
+#define NVB06F_WFI (0x00000078)
+#define NVB06F_WFI_SCOPE 0:0
+#define NVB06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000
+#define NVB06F_WFI_SCOPE_ALL 0x00000001
+#define NVB06F_CRC_CHECK (0x0000007c)
+#define NVB06F_CRC_CHECK_VALUE 31:0
+#define NVB06F_YIELD (0x00000080)
+#define NVB06F_YIELD_OP 1:0
+#define NVB06F_YIELD_OP_NOP 0x00000000
+#define NVB06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001
+#define NVB06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002
+#define NVB06F_YIELD_OP_TSG 0x00000003
+
+
+/* GPFIFO entry format */
+#define NVB06F_GP_ENTRY__SIZE 8
+#define NVB06F_GP_ENTRY0_FETCH 0:0
+#define NVB06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
+#define NVB06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
+#define NVB06F_GP_ENTRY0_GET 31:2
+#define NVB06F_GP_ENTRY0_OPERAND 31:0
+#define NVB06F_GP_ENTRY1_GET_HI 7:0
+#define NVB06F_GP_ENTRY1_PRIV 8:8
+#define NVB06F_GP_ENTRY1_PRIV_USER 0x00000000
+#define NVB06F_GP_ENTRY1_PRIV_KERNEL 0x00000001
+#define NVB06F_GP_ENTRY1_LEVEL 9:9
+#define NVB06F_GP_ENTRY1_LEVEL_MAIN 0x00000000
+#define NVB06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
+#define NVB06F_GP_ENTRY1_LENGTH 30:10
+#define NVB06F_GP_ENTRY1_SYNC 31:31
+#define NVB06F_GP_ENTRY1_SYNC_PROCEED 0x00000000
+#define NVB06F_GP_ENTRY1_SYNC_WAIT 0x00000001
+#define NVB06F_GP_ENTRY1_OPCODE 7:0
+#define NVB06F_GP_ENTRY1_OPCODE_NOP 0x00000000
+#define NVB06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
+#define NVB06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
+#define NVB06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
+
+/* dma method formats */
+#define NVB06F_DMA_METHOD_ADDRESS_OLD 12:2
+#define NVB06F_DMA_METHOD_ADDRESS 11:0
+#define NVB06F_DMA_SUBDEVICE_MASK 15:4
+#define NVB06F_DMA_METHOD_SUBCHANNEL 15:13
+#define NVB06F_DMA_TERT_OP 17:16
+#define NVB06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
+#define NVB06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
+#define NVB06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
+#define NVB06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
+#define NVB06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
+#define NVB06F_DMA_METHOD_COUNT_OLD 28:18
+#define NVB06F_DMA_METHOD_COUNT 28:16
+#define NVB06F_DMA_IMMD_DATA 28:16
+#define NVB06F_DMA_SEC_OP 31:29
+#define NVB06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
+#define NVB06F_DMA_SEC_OP_INC_METHOD (0x00000001)
+#define NVB06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
+#define NVB06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
+#define NVB06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
+#define NVB06F_DMA_SEC_OP_ONE_INC (0x00000005)
+#define NVB06F_DMA_SEC_OP_RESERVED6 (0x00000006)
+#define NVB06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
+/* dma incrementing method format */
+#define NVB06F_DMA_INCR_ADDRESS 11:0
+#define NVB06F_DMA_INCR_SUBCHANNEL 15:13
+#define NVB06F_DMA_INCR_COUNT 28:16
+#define NVB06F_DMA_INCR_OPCODE 31:29
+#define NVB06F_DMA_INCR_OPCODE_VALUE (0x00000001)
+#define NVB06F_DMA_INCR_DATA 31:0
+/* dma non-incrementing method format */
+#define NVB06F_DMA_NONINCR_ADDRESS 11:0
+#define NVB06F_DMA_NONINCR_SUBCHANNEL 15:13
+#define NVB06F_DMA_NONINCR_COUNT 28:16
+#define NVB06F_DMA_NONINCR_OPCODE 31:29
+#define NVB06F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
+#define NVB06F_DMA_NONINCR_DATA 31:0
+/* dma increment-once method format */
+#define NVB06F_DMA_ONEINCR_ADDRESS 11:0
+#define NVB06F_DMA_ONEINCR_SUBCHANNEL 15:13
+#define NVB06F_DMA_ONEINCR_COUNT 28:16
+#define NVB06F_DMA_ONEINCR_OPCODE 31:29
+#define NVB06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
+#define NVB06F_DMA_ONEINCR_DATA 31:0
+/* dma no-operation format */
+#define NVB06F_DMA_NOP (0x00000000)
+/* dma immediate-data format */
+#define NVB06F_DMA_IMMD_ADDRESS 11:0
+#define NVB06F_DMA_IMMD_SUBCHANNEL 15:13
+#define NVB06F_DMA_IMMD_DATA 28:16
+#define NVB06F_DMA_IMMD_OPCODE 31:29
+#define NVB06F_DMA_IMMD_OPCODE_VALUE (0x00000004)
+/* dma set sub-device mask format */
+#define NVB06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NVB06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
+#define NVB06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
+/* dma store sub-device mask format */
+#define NVB06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
+#define NVB06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVB06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
+/* dma use sub-device mask format */
+#define NVB06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVB06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
+/* dma end-segment format */
+#define NVB06F_DMA_ENDSEG_OPCODE 31:29
+#define NVB06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
+/* dma legacy incrementing/non-incrementing formats */
+#define NVB06F_DMA_ADDRESS 12:2
+#define NVB06F_DMA_SUBCH 15:13
+#define NVB06F_DMA_OPCODE3 17:16
+#define NVB06F_DMA_OPCODE3_NONE (0x00000000)
+#define NVB06F_DMA_COUNT 28:18
+#define NVB06F_DMA_OPCODE 31:29
+#define NVB06F_DMA_OPCODE_METHOD (0x00000000)
+#define NVB06F_DMA_OPCODE_NONINC_METHOD (0x00000002)
+#define NVB06F_DMA_DATA 31:0
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _clb06f_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _clc06f_h_
+#define _clc06f_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class PASCAL_CHANNEL_GPFIFO */
+/*
+ * Documentation for PASCAL_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
+ * chapter "User Control Registers". It is documented as device NV_UDMA.
+ * The GPFIFO format itself is also documented in dev_pbdma.ref,
+ * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
+ * chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
+ *
+ * Note there is no .mfs file for this class.
+ */
+#define PASCAL_CHANNEL_GPFIFO_A (0x0000C06F)
+
+#define NVC06F_TYPEDEF PASCAL_CHANNELChannelGPFifoA
+
+/* dma flow control data structure */
+typedef volatile struct Nvc06fControl_struct {
+ NvU32 Ignored00[0x010]; /* 0000-003f*/
+ NvU32 Put; /* put offset, read/write 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 PutHi; /* high order put offset bits 004c-004f*/
+ NvU32 Ignored01[0x002]; /* 0050-0057*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
+ NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
+ NvU32 GetHi; /* high order get offset bits 0060-0063*/
+ NvU32 Ignored02[0x007]; /* 0064-007f*/
+ NvU32 Ignored03; /* used to be engine yield 0080-0083*/
+ NvU32 Ignored04[0x001]; /* 0084-0087*/
+ NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
+ NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
+ NvU32 Ignored05[0x5c];
+} Nvc06fControl, PascalAControlGPFifo;
+
+/* fields and values */
+#define NVC06F_NUMBER_OF_SUBCHANNELS (8)
+#define NVC06F_SET_OBJECT (0x00000000)
+#define NVC06F_SET_OBJECT_NVCLASS 15:0
+#define NVC06F_SET_OBJECT_ENGINE 20:16
+#define NVC06F_SET_OBJECT_ENGINE_SW 0x0000001f
+#define NVC06F_ILLEGAL (0x00000004)
+#define NVC06F_ILLEGAL_HANDLE 31:0
+#define NVC06F_NOP (0x00000008)
+#define NVC06F_NOP_HANDLE 31:0
+#define NVC06F_SEMAPHOREA (0x00000010)
+#define NVC06F_SEMAPHOREA_OFFSET_UPPER 7:0
+#define NVC06F_SEMAPHOREB (0x00000014)
+#define NVC06F_SEMAPHOREB_OFFSET_LOWER 31:2
+#define NVC06F_SEMAPHOREC (0x00000018)
+#define NVC06F_SEMAPHOREC_PAYLOAD 31:0
+#define NVC06F_SEMAPHORED (0x0000001C)
+#define NVC06F_SEMAPHORED_OPERATION 4:0
+#define NVC06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
+#define NVC06F_SEMAPHORED_OPERATION_RELEASE 0x00000002
+#define NVC06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
+#define NVC06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
+#define NVC06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010
+#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH 12:12
+#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
+#define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
+#define NVC06F_SEMAPHORED_RELEASE_WFI 20:20
+#define NVC06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
+#define NVC06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
+#define NVC06F_SEMAPHORED_RELEASE_SIZE 24:24
+#define NVC06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
+#define NVC06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
+#define NVC06F_SEMAPHORED_REDUCTION 30:27
+#define NVC06F_SEMAPHORED_REDUCTION_MIN 0x00000000
+#define NVC06F_SEMAPHORED_REDUCTION_MAX 0x00000001
+#define NVC06F_SEMAPHORED_REDUCTION_XOR 0x00000002
+#define NVC06F_SEMAPHORED_REDUCTION_AND 0x00000003
+#define NVC06F_SEMAPHORED_REDUCTION_OR 0x00000004
+#define NVC06F_SEMAPHORED_REDUCTION_ADD 0x00000005
+#define NVC06F_SEMAPHORED_REDUCTION_INC 0x00000006
+#define NVC06F_SEMAPHORED_REDUCTION_DEC 0x00000007
+#define NVC06F_SEMAPHORED_FORMAT 31:31
+#define NVC06F_SEMAPHORED_FORMAT_SIGNED 0x00000000
+#define NVC06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001
+#define NVC06F_NON_STALL_INTERRUPT (0x00000020)
+#define NVC06F_NON_STALL_INTERRUPT_HANDLE 31:0
+#define NVC06F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR
+#define NVC06F_FB_FLUSH_HANDLE 31:0
+// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
+// specifying the page address for a targeted TLB invalidate and the uTLB for
+// a targeted REPLAY_CANCEL for UVM.
+// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly
+// rearranged fields.
+#define NVC06F_MEM_OP_A (0x00000028)
+#define NVC06F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED
+#define NVC06F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED
+#define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11
+#define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001
+#define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000
+#define NVC06F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12
+#define NVC06F_MEM_OP_B (0x0000002c)
+#define NVC06F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0
+#define NVC06F_MEM_OP_C (0x00000030)
+#define NVC06F_MEM_OP_C_MEMBAR_TYPE 2:0
+#define NVC06F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000
+#define NVC06F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003
+#define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE
+// MEM_OP_D MUST be preceded by MEM_OPs A-C.
+#define NVC06F_MEM_OP_D (0x00000034)
+#define NVC06F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE
+#define NVC06F_MEM_OP_D_OPERATION 31:27
+#define NVC06F_MEM_OP_D_OPERATION_MEMBAR 0x00000005
+#define NVC06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009
+#define NVC06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a
+#define NVC06F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
+#define NVC06F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
+// CLEAN_LINES is an alias for Tegra/GPU IP usage
+#define NVC06F_MEM_OP_D_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e
+// This B alias is confusing but it was missed as part of the update. Left here
+// for compatibility.
+#define NVC06F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e
+#define NVC06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
+#define NVC06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010
+#define NVC06F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015
+#define NVC06F_SET_REFERENCE (0x00000050)
+#define NVC06F_SET_REFERENCE_COUNT 31:0
+// Syncpoint methods are only available on Tegra parts. Attempting to use
+// them on discrete GPUs will result in Host raising NV_PPBDMA_INTR_0_METHOD.
+#define NVC06F_SYNCPOINTA (0x00000070)
+#define NVC06F_SYNCPOINTA_PAYLOAD 31:0
+#define NVC06F_SYNCPOINTB (0x00000074)
+#define NVC06F_SYNCPOINTB_OPERATION 0:0
+#define NVC06F_SYNCPOINTB_OPERATION_WAIT 0x00000000
+#define NVC06F_SYNCPOINTB_OPERATION_INCR 0x00000001
+#define NVC06F_SYNCPOINTB_WAIT_SWITCH 4:4
+#define NVC06F_SYNCPOINTB_WAIT_SWITCH_DIS 0x00000000
+#define NVC06F_SYNCPOINTB_WAIT_SWITCH_EN 0x00000001
+#define NVC06F_SYNCPOINTB_SYNCPT_INDEX 19:8
+#define NVC06F_WFI (0x00000078)
+#define NVC06F_WFI_SCOPE 0:0
+#define NVC06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000
+#define NVC06F_WFI_SCOPE_ALL 0x00000001
+#define NVC06F_CRC_CHECK (0x0000007c)
+#define NVC06F_CRC_CHECK_VALUE 31:0
+#define NVC06F_YIELD (0x00000080)
+#define NVC06F_YIELD_OP 1:0
+#define NVC06F_YIELD_OP_NOP 0x00000000
+#define NVC06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001
+#define NVC06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002
+#define NVC06F_YIELD_OP_TSG 0x00000003
+
+
+/* GPFIFO entry format */
+#define NVC06F_GP_ENTRY__SIZE 8
+#define NVC06F_GP_ENTRY0_FETCH 0:0
+#define NVC06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
+#define NVC06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
+#define NVC06F_GP_ENTRY0_GET 31:2
+#define NVC06F_GP_ENTRY0_OPERAND 31:0
+#define NVC06F_GP_ENTRY1_GET_HI 7:0
+#define NVC06F_GP_ENTRY1_PRIV 8:8
+#define NVC06F_GP_ENTRY1_PRIV_USER 0x00000000
+#define NVC06F_GP_ENTRY1_PRIV_KERNEL 0x00000001
+#define NVC06F_GP_ENTRY1_LEVEL 9:9
+#define NVC06F_GP_ENTRY1_LEVEL_MAIN 0x00000000
+#define NVC06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
+#define NVC06F_GP_ENTRY1_LENGTH 30:10
+#define NVC06F_GP_ENTRY1_SYNC 31:31
+#define NVC06F_GP_ENTRY1_SYNC_PROCEED 0x00000000
+#define NVC06F_GP_ENTRY1_SYNC_WAIT 0x00000001
+#define NVC06F_GP_ENTRY1_OPCODE 7:0
+#define NVC06F_GP_ENTRY1_OPCODE_NOP 0x00000000
+#define NVC06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
+#define NVC06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
+#define NVC06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
+
+/* dma method formats */
+#define NVC06F_DMA_METHOD_ADDRESS_OLD 12:2
+#define NVC06F_DMA_METHOD_ADDRESS 11:0
+#define NVC06F_DMA_SUBDEVICE_MASK 15:4
+#define NVC06F_DMA_METHOD_SUBCHANNEL 15:13
+#define NVC06F_DMA_TERT_OP 17:16
+#define NVC06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
+#define NVC06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
+#define NVC06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
+#define NVC06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
+#define NVC06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
+#define NVC06F_DMA_METHOD_COUNT_OLD 28:18
+#define NVC06F_DMA_METHOD_COUNT 28:16
+#define NVC06F_DMA_IMMD_DATA 28:16
+#define NVC06F_DMA_SEC_OP 31:29
+#define NVC06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
+#define NVC06F_DMA_SEC_OP_INC_METHOD (0x00000001)
+#define NVC06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
+#define NVC06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
+#define NVC06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
+#define NVC06F_DMA_SEC_OP_ONE_INC (0x00000005)
+#define NVC06F_DMA_SEC_OP_RESERVED6 (0x00000006)
+#define NVC06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
+/* dma incrementing method format */
+#define NVC06F_DMA_INCR_ADDRESS 11:0
+#define NVC06F_DMA_INCR_SUBCHANNEL 15:13
+#define NVC06F_DMA_INCR_COUNT 28:16
+#define NVC06F_DMA_INCR_OPCODE 31:29
+#define NVC06F_DMA_INCR_OPCODE_VALUE (0x00000001)
+#define NVC06F_DMA_INCR_DATA 31:0
+/* dma non-incrementing method format */
+#define NVC06F_DMA_NONINCR_ADDRESS 11:0
+#define NVC06F_DMA_NONINCR_SUBCHANNEL 15:13
+#define NVC06F_DMA_NONINCR_COUNT 28:16
+#define NVC06F_DMA_NONINCR_OPCODE 31:29
+#define NVC06F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
+#define NVC06F_DMA_NONINCR_DATA 31:0
+/* dma increment-once method format */
+#define NVC06F_DMA_ONEINCR_ADDRESS 11:0
+#define NVC06F_DMA_ONEINCR_SUBCHANNEL 15:13
+#define NVC06F_DMA_ONEINCR_COUNT 28:16
+#define NVC06F_DMA_ONEINCR_OPCODE 31:29
+#define NVC06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
+#define NVC06F_DMA_ONEINCR_DATA 31:0
+/* dma no-operation format */
+#define NVC06F_DMA_NOP (0x00000000)
+/* dma immediate-data format */
+#define NVC06F_DMA_IMMD_ADDRESS 11:0
+#define NVC06F_DMA_IMMD_SUBCHANNEL 15:13
+#define NVC06F_DMA_IMMD_DATA 28:16
+#define NVC06F_DMA_IMMD_OPCODE 31:29
+#define NVC06F_DMA_IMMD_OPCODE_VALUE (0x00000004)
+/* dma set sub-device mask format */
+#define NVC06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
+/* dma store sub-device mask format */
+#define NVC06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
+#define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
+/* dma use sub-device mask format */
+#define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
+/* dma end-segment format */
+#define NVC06F_DMA_ENDSEG_OPCODE 31:29
+#define NVC06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
+/* dma legacy incrementing/non-incrementing formats */
+#define NVC06F_DMA_ADDRESS 12:2
+#define NVC06F_DMA_SUBCH 15:13
+#define NVC06F_DMA_OPCODE3 17:16
+#define NVC06F_DMA_OPCODE3_NONE (0x00000000)
+#define NVC06F_DMA_COUNT 28:18
+#define NVC06F_DMA_OPCODE 31:29
+#define NVC06F_DMA_OPCODE_METHOD (0x00000000)
+#define NVC06F_DMA_OPCODE_NONINC_METHOD (0x00000002)
+#define NVC06F_DMA_DATA 31:0
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _clc06f_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _clc36f_h_
+#define _clc36f_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class VOLTA_CHANNEL_GPFIFO */
+/*
+ * Documentation for VOLTA_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
+ * chapter "User Control Registers". It is documented as device NV_UDMA.
+ * The GPFIFO format itself is also documented in dev_pbdma.ref,
+ * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
+ * chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
+ *
+ * Note there is no .mfs file for this class.
+ */
+#define VOLTA_CHANNEL_GPFIFO_A (0x0000C36F)
+
+#define NVC36F_TYPEDEF VOLTA_CHANNELChannelGPFifoA
+
+/* dma flow control data structure */
+typedef volatile struct Nvc36fControl_struct {
+ NvU32 Ignored00[0x010]; /* 0000-003f*/
+ NvU32 Put; /* put offset, read/write 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 PutHi; /* high order put offset bits 004c-004f*/
+ NvU32 Ignored01[0x002]; /* 0050-0057*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
+ NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
+ NvU32 GetHi; /* high order get offset bits 0060-0063*/
+ NvU32 Ignored02[0x007]; /* 0064-007f*/
+ NvU32 Ignored03; /* used to be engine yield 0080-0083*/
+ NvU32 Ignored04[0x001]; /* 0084-0087*/
+ NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
+ NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
+ NvU32 Ignored05[0x5c];
+} Nvc36fControl, VoltaAControlGPFifo;
+
+/* fields and values */
+#define NVC36F_NUMBER_OF_SUBCHANNELS (8)
+#define NVC36F_SET_OBJECT (0x00000000)
+#define NVC36F_SET_OBJECT_NVCLASS 15:0
+#define NVC36F_SET_OBJECT_ENGINE 20:16
+#define NVC36F_SET_OBJECT_ENGINE_SW 0x0000001f
+#define NVC36F_ILLEGAL (0x00000004)
+#define NVC36F_ILLEGAL_HANDLE 31:0
+#define NVC36F_NOP (0x00000008)
+#define NVC36F_NOP_HANDLE 31:0
+#define NVC36F_SEMAPHOREA (0x00000010)
+#define NVC36F_SEMAPHOREA_OFFSET_UPPER 7:0
+#define NVC36F_SEMAPHOREB (0x00000014)
+#define NVC36F_SEMAPHOREB_OFFSET_LOWER 31:2
+#define NVC36F_SEMAPHOREC (0x00000018)
+#define NVC36F_SEMAPHOREC_PAYLOAD 31:0
+#define NVC36F_SEMAPHORED (0x0000001C)
+#define NVC36F_SEMAPHORED_OPERATION 4:0
+#define NVC36F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
+#define NVC36F_SEMAPHORED_OPERATION_RELEASE 0x00000002
+#define NVC36F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
+#define NVC36F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
+#define NVC36F_SEMAPHORED_OPERATION_REDUCTION 0x00000010
+#define NVC36F_SEMAPHORED_ACQUIRE_SWITCH 12:12
+#define NVC36F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
+#define NVC36F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
+#define NVC36F_SEMAPHORED_RELEASE_WFI 20:20
+#define NVC36F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
+#define NVC36F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
+#define NVC36F_SEMAPHORED_RELEASE_SIZE 24:24
+#define NVC36F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
+#define NVC36F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
+#define NVC36F_SEMAPHORED_REDUCTION 30:27
+#define NVC36F_SEMAPHORED_REDUCTION_MIN 0x00000000
+#define NVC36F_SEMAPHORED_REDUCTION_MAX 0x00000001
+#define NVC36F_SEMAPHORED_REDUCTION_XOR 0x00000002
+#define NVC36F_SEMAPHORED_REDUCTION_AND 0x00000003
+#define NVC36F_SEMAPHORED_REDUCTION_OR 0x00000004
+#define NVC36F_SEMAPHORED_REDUCTION_ADD 0x00000005
+#define NVC36F_SEMAPHORED_REDUCTION_INC 0x00000006
+#define NVC36F_SEMAPHORED_REDUCTION_DEC 0x00000007
+#define NVC36F_SEMAPHORED_FORMAT 31:31
+#define NVC36F_SEMAPHORED_FORMAT_SIGNED 0x00000000
+#define NVC36F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001
+#define NVC36F_NON_STALL_INTERRUPT (0x00000020)
+#define NVC36F_NON_STALL_INTERRUPT_HANDLE 31:0
+#define NVC36F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR
+#define NVC36F_FB_FLUSH_HANDLE 31:0
+// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
+// specifying the page address for a targeted TLB invalidate and the uTLB for
+// a targeted REPLAY_CANCEL for UVM.
+// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly
+// rearranged fields.
+#define NVC36F_MEM_OP_A (0x00000028)
+#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED
+#define NVC36F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type
+#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED
+#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL
+#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11
+#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001
+#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000
+#define NVC36F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12
+#define NVC36F_MEM_OP_B (0x0000002c)
+#define NVC36F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0
+#define NVC36F_MEM_OP_C (0x00000030)
+#define NVC36F_MEM_OP_C_MEMBAR_TYPE 2:0
+#define NVC36F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000
+#define NVC36F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003
+#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE
+#define NVC36F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0
+// MEM_OP_D MUST be preceded by MEM_OPs A-C.
+#define NVC36F_MEM_OP_D (0x00000034)
+#define NVC36F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE
+#define NVC36F_MEM_OP_D_OPERATION 31:27
+#define NVC36F_MEM_OP_D_OPERATION_MEMBAR 0x00000005
+#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009
+#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a
+#define NVC36F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
+#define NVC36F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
+// CLEAN_LINES is an alias for Tegra/GPU IP usage
+#define NVC36F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e
+#define NVC36F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
+#define NVC36F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010
+#define NVC36F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015
+#define NVC36F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016
+#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0
+#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000
+#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001
+#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002
+#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003
+#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2
+#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000
+#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001
+#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3
+#define NVC36F_SET_REFERENCE (0x00000050)
+#define NVC36F_SET_REFERENCE_COUNT 31:0
+#define NVC36F_SEM_ADDR_LO (0x0000005c)
+#define NVC36F_SEM_ADDR_LO_OFFSET 31:2
+#define NVC36F_SEM_ADDR_HI (0x00000060)
+#define NVC36F_SEM_ADDR_HI_OFFSET 7:0
+#define NVC36F_SEM_PAYLOAD_LO (0x00000064)
+#define NVC36F_SEM_PAYLOAD_LO_PAYLOAD 31:0
+#define NVC36F_SEM_PAYLOAD_HI (0x00000068)
+#define NVC36F_SEM_PAYLOAD_HI_PAYLOAD 31:0
+#define NVC36F_SEM_EXECUTE (0x0000006c)
+#define NVC36F_SEM_EXECUTE_OPERATION 2:0
+#define NVC36F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000
+#define NVC36F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
+#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002
+#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003
+#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004
+#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005
+#define NVC36F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006
+#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12
+#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000
+#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001
+#define NVC36F_SEM_EXECUTE_RELEASE_WFI 20:20
+#define NVC36F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
+#define NVC36F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001
+#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
+#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
+#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001
+#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25
+#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000
+#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001
+#define NVC36F_SEM_EXECUTE_REDUCTION 30:27
+#define NVC36F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000
+#define NVC36F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001
+#define NVC36F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002
+#define NVC36F_SEM_EXECUTE_REDUCTION_IAND 0x00000003
+#define NVC36F_SEM_EXECUTE_REDUCTION_IOR 0x00000004
+#define NVC36F_SEM_EXECUTE_REDUCTION_IADD 0x00000005
+#define NVC36F_SEM_EXECUTE_REDUCTION_INC 0x00000006
+#define NVC36F_SEM_EXECUTE_REDUCTION_DEC 0x00000007
+#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT 31:31
+#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000
+#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001
+#define NVC36F_WFI (0x00000078)
+#define NVC36F_WFI_SCOPE 0:0
+#define NVC36F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000
+#define NVC36F_WFI_SCOPE_CURRENT_VEID 0x00000000
+#define NVC36F_WFI_SCOPE_ALL 0x00000001
+#define NVC36F_CRC_CHECK (0x0000007c)
+#define NVC36F_CRC_CHECK_VALUE 31:0
+#define NVC36F_YIELD (0x00000080)
+#define NVC36F_YIELD_OP 1:0
+#define NVC36F_YIELD_OP_NOP 0x00000000
+#define NVC36F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002
+#define NVC36F_YIELD_OP_TSG 0x00000003
+#define NVC36F_CLEAR_FAULTED (0x00000084)
+#define NVC36F_CLEAR_FAULTED_CHID 11:0
+#define NVC36F_CLEAR_FAULTED_TYPE 31:31
+#define NVC36F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000
+#define NVC36F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001
+
+
+/* GPFIFO entry format */
+#define NVC36F_GP_ENTRY__SIZE 8
+#define NVC36F_GP_ENTRY0_FETCH 0:0
+#define NVC36F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
+#define NVC36F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
+#define NVC36F_GP_ENTRY0_GET 31:2
+#define NVC36F_GP_ENTRY0_OPERAND 31:0
+#define NVC36F_GP_ENTRY1_GET_HI 7:0
+#define NVC36F_GP_ENTRY1_PRIV 8:8
+#define NVC36F_GP_ENTRY1_PRIV_USER 0x00000000
+#define NVC36F_GP_ENTRY1_PRIV_KERNEL 0x00000001
+#define NVC36F_GP_ENTRY1_LEVEL 9:9
+#define NVC36F_GP_ENTRY1_LEVEL_MAIN 0x00000000
+#define NVC36F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
+#define NVC36F_GP_ENTRY1_LENGTH 30:10
+#define NVC36F_GP_ENTRY1_SYNC 31:31
+#define NVC36F_GP_ENTRY1_SYNC_PROCEED 0x00000000
+#define NVC36F_GP_ENTRY1_SYNC_WAIT 0x00000001
+#define NVC36F_GP_ENTRY1_OPCODE 7:0
+#define NVC36F_GP_ENTRY1_OPCODE_NOP 0x00000000
+#define NVC36F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
+#define NVC36F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
+#define NVC36F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
+
+/* dma method formats */
+#define NVC36F_DMA_METHOD_ADDRESS_OLD 12:2
+#define NVC36F_DMA_METHOD_ADDRESS 11:0
+#define NVC36F_DMA_SUBDEVICE_MASK 15:4
+#define NVC36F_DMA_METHOD_SUBCHANNEL 15:13
+#define NVC36F_DMA_TERT_OP 17:16
+#define NVC36F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
+#define NVC36F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
+#define NVC36F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
+#define NVC36F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
+#define NVC36F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
+#define NVC36F_DMA_METHOD_COUNT_OLD 28:18
+#define NVC36F_DMA_METHOD_COUNT 28:16
+#define NVC36F_DMA_IMMD_DATA 28:16
+#define NVC36F_DMA_SEC_OP 31:29
+#define NVC36F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
+#define NVC36F_DMA_SEC_OP_INC_METHOD (0x00000001)
+#define NVC36F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
+#define NVC36F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
+#define NVC36F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
+#define NVC36F_DMA_SEC_OP_ONE_INC (0x00000005)
+#define NVC36F_DMA_SEC_OP_RESERVED6 (0x00000006)
+#define NVC36F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
+/* dma incrementing method format */
+#define NVC36F_DMA_INCR_ADDRESS 11:0
+#define NVC36F_DMA_INCR_SUBCHANNEL 15:13
+#define NVC36F_DMA_INCR_COUNT 28:16
+#define NVC36F_DMA_INCR_OPCODE 31:29
+#define NVC36F_DMA_INCR_OPCODE_VALUE (0x00000001)
+#define NVC36F_DMA_INCR_DATA 31:0
+/* dma non-incrementing method format */
+#define NVC36F_DMA_NONINCR_ADDRESS 11:0
+#define NVC36F_DMA_NONINCR_SUBCHANNEL 15:13
+#define NVC36F_DMA_NONINCR_COUNT 28:16
+#define NVC36F_DMA_NONINCR_OPCODE 31:29
+#define NVC36F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
+#define NVC36F_DMA_NONINCR_DATA 31:0
+/* dma increment-once method format */
+#define NVC36F_DMA_ONEINCR_ADDRESS 11:0
+#define NVC36F_DMA_ONEINCR_SUBCHANNEL 15:13
+#define NVC36F_DMA_ONEINCR_COUNT 28:16
+#define NVC36F_DMA_ONEINCR_OPCODE 31:29
+#define NVC36F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
+#define NVC36F_DMA_ONEINCR_DATA 31:0
+/* dma no-operation format */
+#define NVC36F_DMA_NOP (0x00000000)
+/* dma immediate-data format */
+#define NVC36F_DMA_IMMD_ADDRESS 11:0
+#define NVC36F_DMA_IMMD_SUBCHANNEL 15:13
+#define NVC36F_DMA_IMMD_DATA 28:16
+#define NVC36F_DMA_IMMD_OPCODE 31:29
+#define NVC36F_DMA_IMMD_OPCODE_VALUE (0x00000004)
+/* dma set sub-device mask format */
+#define NVC36F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NVC36F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC36F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
+/* dma store sub-device mask format */
+#define NVC36F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
+#define NVC36F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC36F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
+/* dma use sub-device mask format */
+#define NVC36F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC36F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
+/* dma end-segment format */
+#define NVC36F_DMA_ENDSEG_OPCODE 31:29
+#define NVC36F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
+/* dma legacy incrementing/non-incrementing formats */
+#define NVC36F_DMA_ADDRESS 12:2
+#define NVC36F_DMA_SUBCH 15:13
+#define NVC36F_DMA_OPCODE3 17:16
+#define NVC36F_DMA_OPCODE3_NONE (0x00000000)
+#define NVC36F_DMA_COUNT 28:18
+#define NVC36F_DMA_OPCODE 31:29
+#define NVC36F_DMA_OPCODE_METHOD (0x00000000)
+#define NVC36F_DMA_OPCODE_NONINC_METHOD (0x00000002)
+#define NVC36F_DMA_DATA 31:0
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _clc36f_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _clc46f_h_
+#define _clc46f_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class TURING_CHANNEL_GPFIFO */
+/*
+ * Documentation for TURING_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
+ * chapter "User Control Registers". It is documented as device NV_UDMA.
+ * The GPFIFO format itself is also documented in dev_pbdma.ref,
+ * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
+ * chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
+ *
+ * Note there is no .mfs file for this class.
+ */
+#define TURING_CHANNEL_GPFIFO_A (0x0000C46F)
+
+#define NVC46F_TYPEDEF TURING_CHANNELChannelGPFifoA
+
+/* dma flow control data structure */
+typedef volatile struct Nvc46fControl_struct {
+ NvU32 Ignored00[0x010]; /* 0000-003f*/
+ NvU32 Put; /* put offset, read/write 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 PutHi; /* high order put offset bits 004c-004f*/
+ NvU32 Ignored01[0x002]; /* 0050-0057*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
+ NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
+ NvU32 GetHi; /* high order get offset bits 0060-0063*/
+ NvU32 Ignored02[0x007]; /* 0064-007f*/
+ NvU32 Ignored03; /* used to be engine yield 0080-0083*/
+ NvU32 Ignored04[0x001]; /* 0084-0087*/
+ NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
+ NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
+ NvU32 Ignored05[0x5c];
+} Nvc46fControl, TuringAControlGPFifo;
+
+/* fields and values */
+#define NVC46F_NUMBER_OF_SUBCHANNELS (8)
+#define NVC46F_SET_OBJECT (0x00000000)
+#define NVC46F_SET_OBJECT_NVCLASS 15:0
+#define NVC46F_SET_OBJECT_ENGINE 20:16
+#define NVC46F_SET_OBJECT_ENGINE_SW 0x0000001f
+#define NVC46F_ILLEGAL (0x00000004)
+#define NVC46F_ILLEGAL_HANDLE 31:0
+#define NVC46F_NOP (0x00000008)
+#define NVC46F_NOP_HANDLE 31:0
+#define NVC46F_SEMAPHOREA (0x00000010)
+#define NVC46F_SEMAPHOREA_OFFSET_UPPER 7:0
+#define NVC46F_SEMAPHOREB (0x00000014)
+#define NVC46F_SEMAPHOREB_OFFSET_LOWER 31:2
+#define NVC46F_SEMAPHOREC (0x00000018)
+#define NVC46F_SEMAPHOREC_PAYLOAD 31:0
+#define NVC46F_SEMAPHORED (0x0000001C)
+#define NVC46F_SEMAPHORED_OPERATION 4:0
+#define NVC46F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
+#define NVC46F_SEMAPHORED_OPERATION_RELEASE 0x00000002
+#define NVC46F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
+#define NVC46F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
+#define NVC46F_SEMAPHORED_OPERATION_REDUCTION 0x00000010
+#define NVC46F_SEMAPHORED_ACQUIRE_SWITCH 12:12
+#define NVC46F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
+#define NVC46F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
+#define NVC46F_SEMAPHORED_RELEASE_WFI 20:20
+#define NVC46F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
+#define NVC46F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
+#define NVC46F_SEMAPHORED_RELEASE_SIZE 24:24
+#define NVC46F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
+#define NVC46F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
+#define NVC46F_SEMAPHORED_REDUCTION 30:27
+#define NVC46F_SEMAPHORED_REDUCTION_MIN 0x00000000
+#define NVC46F_SEMAPHORED_REDUCTION_MAX 0x00000001
+#define NVC46F_SEMAPHORED_REDUCTION_XOR 0x00000002
+#define NVC46F_SEMAPHORED_REDUCTION_AND 0x00000003
+#define NVC46F_SEMAPHORED_REDUCTION_OR 0x00000004
+#define NVC46F_SEMAPHORED_REDUCTION_ADD 0x00000005
+#define NVC46F_SEMAPHORED_REDUCTION_INC 0x00000006
+#define NVC46F_SEMAPHORED_REDUCTION_DEC 0x00000007
+#define NVC46F_SEMAPHORED_FORMAT 31:31
+#define NVC46F_SEMAPHORED_FORMAT_SIGNED 0x00000000
+#define NVC46F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001
+#define NVC46F_NON_STALL_INTERRUPT (0x00000020)
+#define NVC46F_NON_STALL_INTERRUPT_HANDLE 31:0
+#define NVC46F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR
+#define NVC46F_FB_FLUSH_HANDLE 31:0
+// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
+// specifying the page address for a targeted TLB invalidate and the uTLB for
+// a targeted REPLAY_CANCEL for UVM.
+// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly
+// rearranged fields.
+#define NVC46F_MEM_OP_A (0x00000028)
+#define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED
+#define NVC46F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type
+#define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED
+#define NVC46F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL
+#define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11
+#define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001
+#define NVC46F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000
+#define NVC46F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12
+#define NVC46F_MEM_OP_B (0x0000002c)
+#define NVC46F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0
+#define NVC46F_MEM_OP_C (0x00000030)
+#define NVC46F_MEM_OP_C_MEMBAR_TYPE 2:0
+#define NVC46F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000
+#define NVC46F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003
+#define NVC46F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE
+#define NVC46F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0
+// MEM_OP_D MUST be preceded by MEM_OPs A-C.
+#define NVC46F_MEM_OP_D (0x00000034)
+#define NVC46F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE
+#define NVC46F_MEM_OP_D_OPERATION 31:27
+#define NVC46F_MEM_OP_D_OPERATION_MEMBAR 0x00000005
+#define NVC46F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009
+#define NVC46F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a
+#define NVC46F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
+#define NVC46F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
+// CLEAN_LINES is an alias for Tegra/GPU IP usage
+#define NVC46F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e
+#define NVC46F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
+#define NVC46F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010
+#define NVC46F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015
+#define NVC46F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016
+#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0
+#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000
+#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001
+#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002
+#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003
+#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2
+#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000
+#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001
+#define NVC46F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3
+#define NVC46F_SET_REFERENCE (0x00000050)
+#define NVC46F_SET_REFERENCE_COUNT 31:0
+#define NVC46F_SEM_ADDR_LO (0x0000005c)
+#define NVC46F_SEM_ADDR_LO_OFFSET 31:2
+#define NVC46F_SEM_ADDR_HI (0x00000060)
+#define NVC46F_SEM_ADDR_HI_OFFSET 7:0
+#define NVC46F_SEM_PAYLOAD_LO (0x00000064)
+#define NVC46F_SEM_PAYLOAD_LO_PAYLOAD 31:0
+#define NVC46F_SEM_PAYLOAD_HI (0x00000068)
+#define NVC46F_SEM_PAYLOAD_HI_PAYLOAD 31:0
+#define NVC46F_SEM_EXECUTE (0x0000006c)
+#define NVC46F_SEM_EXECUTE_OPERATION 2:0
+#define NVC46F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000
+#define NVC46F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
+#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002
+#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003
+#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004
+#define NVC46F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005
+#define NVC46F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006
+#define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12
+#define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000
+#define NVC46F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001
+#define NVC46F_SEM_EXECUTE_RELEASE_WFI 20:20
+#define NVC46F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
+#define NVC46F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001
+#define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
+#define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
+#define NVC46F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001
+#define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25
+#define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000
+#define NVC46F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001
+#define NVC46F_SEM_EXECUTE_REDUCTION 30:27
+#define NVC46F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000
+#define NVC46F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001
+#define NVC46F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002
+#define NVC46F_SEM_EXECUTE_REDUCTION_IAND 0x00000003
+#define NVC46F_SEM_EXECUTE_REDUCTION_IOR 0x00000004
+#define NVC46F_SEM_EXECUTE_REDUCTION_IADD 0x00000005
+#define NVC46F_SEM_EXECUTE_REDUCTION_INC 0x00000006
+#define NVC46F_SEM_EXECUTE_REDUCTION_DEC 0x00000007
+#define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT 31:31
+#define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000
+#define NVC46F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001
+#define NVC46F_WFI (0x00000078)
+#define NVC46F_WFI_SCOPE 0:0
+#define NVC46F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000
+#define NVC46F_WFI_SCOPE_CURRENT_VEID 0x00000000
+#define NVC46F_WFI_SCOPE_ALL 0x00000001
+#define NVC46F_CRC_CHECK (0x0000007c)
+#define NVC46F_CRC_CHECK_VALUE 31:0
+#define NVC46F_YIELD (0x00000080)
+#define NVC46F_YIELD_OP 1:0
+#define NVC46F_YIELD_OP_NOP 0x00000000
+#define NVC46F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002
+#define NVC46F_YIELD_OP_TSG 0x00000003
+#define NVC46F_CLEAR_FAULTED (0x00000084)
+// Note: RM provides the HANDLE as an opaque value; the internal detail fields
+// are intentionally not exposed to the driver through these defines.
+#define NVC46F_CLEAR_FAULTED_HANDLE 30:0
+#define NVC46F_CLEAR_FAULTED_TYPE 31:31
+#define NVC46F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000
+#define NVC46F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001
+
+
+/* GPFIFO entry format */
+#define NVC46F_GP_ENTRY__SIZE 8
+#define NVC46F_GP_ENTRY0_FETCH 0:0
+#define NVC46F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
+#define NVC46F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
+#define NVC46F_GP_ENTRY0_GET 31:2
+#define NVC46F_GP_ENTRY0_OPERAND 31:0
+#define NVC46F_GP_ENTRY1_GET_HI 7:0
+#define NVC46F_GP_ENTRY1_LEVEL 9:9
+#define NVC46F_GP_ENTRY1_LEVEL_MAIN 0x00000000
+#define NVC46F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
+#define NVC46F_GP_ENTRY1_LENGTH 30:10
+#define NVC46F_GP_ENTRY1_SYNC 31:31
+#define NVC46F_GP_ENTRY1_SYNC_PROCEED 0x00000000
+#define NVC46F_GP_ENTRY1_SYNC_WAIT 0x00000001
+#define NVC46F_GP_ENTRY1_OPCODE 7:0
+#define NVC46F_GP_ENTRY1_OPCODE_NOP 0x00000000
+#define NVC46F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
+#define NVC46F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
+#define NVC46F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
+
+/* dma method formats */
+#define NVC46F_DMA_METHOD_ADDRESS_OLD 12:2
+#define NVC46F_DMA_METHOD_ADDRESS 11:0
+#define NVC46F_DMA_SUBDEVICE_MASK 15:4
+#define NVC46F_DMA_METHOD_SUBCHANNEL 15:13
+#define NVC46F_DMA_TERT_OP 17:16
+#define NVC46F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
+#define NVC46F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
+#define NVC46F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
+#define NVC46F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
+#define NVC46F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
+#define NVC46F_DMA_METHOD_COUNT_OLD 28:18
+#define NVC46F_DMA_METHOD_COUNT 28:16
+#define NVC46F_DMA_IMMD_DATA 28:16
+#define NVC46F_DMA_SEC_OP 31:29
+#define NVC46F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
+#define NVC46F_DMA_SEC_OP_INC_METHOD (0x00000001)
+#define NVC46F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
+#define NVC46F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
+#define NVC46F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
+#define NVC46F_DMA_SEC_OP_ONE_INC (0x00000005)
+#define NVC46F_DMA_SEC_OP_RESERVED6 (0x00000006)
+#define NVC46F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
+/* dma incrementing method format */
+#define NVC46F_DMA_INCR_ADDRESS 11:0
+#define NVC46F_DMA_INCR_SUBCHANNEL 15:13
+#define NVC46F_DMA_INCR_COUNT 28:16
+#define NVC46F_DMA_INCR_OPCODE 31:29
+#define NVC46F_DMA_INCR_OPCODE_VALUE (0x00000001)
+#define NVC46F_DMA_INCR_DATA 31:0
+/* dma non-incrementing method format */
+#define NVC46F_DMA_NONINCR_ADDRESS 11:0
+#define NVC46F_DMA_NONINCR_SUBCHANNEL 15:13
+#define NVC46F_DMA_NONINCR_COUNT 28:16
+#define NVC46F_DMA_NONINCR_OPCODE 31:29
+#define NVC46F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
+#define NVC46F_DMA_NONINCR_DATA 31:0
+/* dma increment-once method format */
+#define NVC46F_DMA_ONEINCR_ADDRESS 11:0
+#define NVC46F_DMA_ONEINCR_SUBCHANNEL 15:13
+#define NVC46F_DMA_ONEINCR_COUNT 28:16
+#define NVC46F_DMA_ONEINCR_OPCODE 31:29
+#define NVC46F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
+#define NVC46F_DMA_ONEINCR_DATA 31:0
+/* dma no-operation format */
+#define NVC46F_DMA_NOP (0x00000000)
+/* dma immediate-data format */
+#define NVC46F_DMA_IMMD_ADDRESS 11:0
+#define NVC46F_DMA_IMMD_SUBCHANNEL 15:13
+#define NVC46F_DMA_IMMD_DATA 28:16
+#define NVC46F_DMA_IMMD_OPCODE 31:29
+#define NVC46F_DMA_IMMD_OPCODE_VALUE (0x00000004)
+/* dma set sub-device mask format */
+#define NVC46F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NVC46F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC46F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
+/* dma store sub-device mask format */
+#define NVC46F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
+#define NVC46F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC46F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
+/* dma use sub-device mask format */
+#define NVC46F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC46F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
+/* dma end-segment format */
+#define NVC46F_DMA_ENDSEG_OPCODE 31:29
+#define NVC46F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
+/* dma legacy incrementing/non-incrementing formats */
+#define NVC46F_DMA_ADDRESS 12:2
+#define NVC46F_DMA_SUBCH 15:13
+#define NVC46F_DMA_OPCODE3 17:16
+#define NVC46F_DMA_OPCODE3_NONE (0x00000000)
+#define NVC46F_DMA_COUNT 28:18
+#define NVC46F_DMA_OPCODE 31:29
+#define NVC46F_DMA_OPCODE_METHOD (0x00000000)
+#define NVC46F_DMA_OPCODE_NONINC_METHOD (0x00000002)
+#define NVC46F_DMA_DATA 31:0
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _clc46f_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _clc56f_h_
+#define _clc56f_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class AMPERE_CHANNEL_GPFIFO */
+/*
+ * Documentation for AMPERE_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
+ * chapter "User Control Registers". It is documented as device NV_UDMA.
+ * The GPFIFO format itself is also documented in dev_pbdma.ref,
+ * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
+ * chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
+ *
+ * Note there is no .mfs file for this class.
+ */
+#define AMPERE_CHANNEL_GPFIFO_A (0x0000C56F)
+
+#define NVC56F_TYPEDEF AMPERE_CHANNELChannelGPFifoA
+
+/* dma flow control data structure */
+typedef volatile struct Nvc56fControl_struct {
+ NvU32 Ignored00[0x010]; /* 0000-003f*/
+ NvU32 Put; /* put offset, read/write 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 PutHi; /* high order put offset bits 004c-004f*/
+ NvU32 Ignored01[0x002]; /* 0050-0057*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
+ NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
+ NvU32 GetHi; /* high order get offset bits 0060-0063*/
+ NvU32 Ignored02[0x007]; /* 0064-007f*/
+ NvU32 Ignored03; /* used to be engine yield 0080-0083*/
+ NvU32 Ignored04[0x001]; /* 0084-0087*/
+ NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
+ NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
+ NvU32 Ignored05[0x5c];
+} Nvc56fControl, AmpereAControlGPFifo;
+
+/* fields and values */
+#define NVC56F_NUMBER_OF_SUBCHANNELS (8)
+#define NVC56F_SET_OBJECT (0x00000000)
+#define NVC56F_SET_OBJECT_NVCLASS 15:0
+#define NVC56F_SET_OBJECT_ENGINE 20:16
+#define NVC56F_SET_OBJECT_ENGINE_SW 0x0000001f
+#define NVC56F_ILLEGAL (0x00000004)
+#define NVC56F_ILLEGAL_HANDLE 31:0
+#define NVC56F_NOP (0x00000008)
+#define NVC56F_NOP_HANDLE 31:0
+#define NVC56F_SEMAPHOREA (0x00000010)
+#define NVC56F_SEMAPHOREA_OFFSET_UPPER 7:0
+#define NVC56F_SEMAPHOREB (0x00000014)
+#define NVC56F_SEMAPHOREB_OFFSET_LOWER 31:2
+#define NVC56F_SEMAPHOREC (0x00000018)
+#define NVC56F_SEMAPHOREC_PAYLOAD 31:0
+#define NVC56F_SEMAPHORED (0x0000001C)
+#define NVC56F_SEMAPHORED_OPERATION 4:0
+#define NVC56F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
+#define NVC56F_SEMAPHORED_OPERATION_RELEASE 0x00000002
+#define NVC56F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
+#define NVC56F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
+#define NVC56F_SEMAPHORED_OPERATION_REDUCTION 0x00000010
+#define NVC56F_SEMAPHORED_ACQUIRE_SWITCH 12:12
+#define NVC56F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
+#define NVC56F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
+#define NVC56F_SEMAPHORED_RELEASE_WFI 20:20
+#define NVC56F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
+#define NVC56F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
+#define NVC56F_SEMAPHORED_RELEASE_SIZE 24:24
+#define NVC56F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
+#define NVC56F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
+#define NVC56F_SEMAPHORED_REDUCTION 30:27
+#define NVC56F_SEMAPHORED_REDUCTION_MIN 0x00000000
+#define NVC56F_SEMAPHORED_REDUCTION_MAX 0x00000001
+#define NVC56F_SEMAPHORED_REDUCTION_XOR 0x00000002
+#define NVC56F_SEMAPHORED_REDUCTION_AND 0x00000003
+#define NVC56F_SEMAPHORED_REDUCTION_OR 0x00000004
+#define NVC56F_SEMAPHORED_REDUCTION_ADD 0x00000005
+#define NVC56F_SEMAPHORED_REDUCTION_INC 0x00000006
+#define NVC56F_SEMAPHORED_REDUCTION_DEC 0x00000007
+#define NVC56F_SEMAPHORED_FORMAT 31:31
+#define NVC56F_SEMAPHORED_FORMAT_SIGNED 0x00000000
+#define NVC56F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001
+#define NVC56F_NON_STALL_INTERRUPT (0x00000020)
+#define NVC56F_NON_STALL_INTERRUPT_HANDLE 31:0
+#define NVC56F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR
+#define NVC56F_FB_FLUSH_HANDLE 31:0
+// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
+// specifying the page address for a targeted TLB invalidate and the uTLB for
+// a targeted REPLAY_CANCEL for UVM.
+// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly
+// rearranged fields.
+#define NVC56F_MEM_OP_A (0x00000028)
+#define NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED
+#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type
+#define NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED
+#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE 7:6 // only relevant for invalidates with NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE for invalidating link TLB only, or non-link TLB only or all TLBs
+#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS 0
+#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS 1
+#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 2
+#define NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD 3
+#define NVC56F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL
+#define NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11
+#define NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001
+#define NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000
+#define NVC56F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12
+#define NVC56F_MEM_OP_B (0x0000002c)
+#define NVC56F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0
+#define NVC56F_MEM_OP_C (0x00000030)
+#define NVC56F_MEM_OP_C_MEMBAR_TYPE 2:0
+#define NVC56F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000
+#define NVC56F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003
+#define NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE
+#define NVC56F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0
+// MEM_OP_D MUST be preceded by MEM_OPs A-C.
+#define NVC56F_MEM_OP_D (0x00000034)
+#define NVC56F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE
+#define NVC56F_MEM_OP_D_OPERATION 31:27
+#define NVC56F_MEM_OP_D_OPERATION_MEMBAR 0x00000005
+#define NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009
+#define NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a
+#define NVC56F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
+#define NVC56F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
+// CLEAN_LINES is an alias for Tegra/GPU IP usage
+#define NVC56F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e
+#define NVC56F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
+#define NVC56F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010
+#define NVC56F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015
+#define NVC56F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016
+#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0
+#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000
+#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001
+#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002
+#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003
+#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2
+#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000
+#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001
+#define NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3
+#define NVC56F_SET_REFERENCE (0x00000050)
+#define NVC56F_SET_REFERENCE_COUNT 31:0
+#define NVC56F_SEM_ADDR_LO (0x0000005c)
+#define NVC56F_SEM_ADDR_LO_OFFSET 31:2
+#define NVC56F_SEM_ADDR_HI (0x00000060)
+#define NVC56F_SEM_ADDR_HI_OFFSET 7:0
+#define NVC56F_SEM_PAYLOAD_LO (0x00000064)
+#define NVC56F_SEM_PAYLOAD_LO_PAYLOAD 31:0
+#define NVC56F_SEM_PAYLOAD_HI (0x00000068)
+#define NVC56F_SEM_PAYLOAD_HI_PAYLOAD 31:0
+#define NVC56F_SEM_EXECUTE (0x0000006c)
+#define NVC56F_SEM_EXECUTE_OPERATION 2:0
+#define NVC56F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000
+#define NVC56F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
+#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002
+#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003
+#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004
+#define NVC56F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005
+#define NVC56F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006
+#define NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12
+#define NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000
+#define NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001
+#define NVC56F_SEM_EXECUTE_RELEASE_WFI 20:20
+#define NVC56F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
+#define NVC56F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001
+#define NVC56F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
+#define NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
+#define NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001
+#define NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25
+#define NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000
+#define NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001
+#define NVC56F_SEM_EXECUTE_REDUCTION 30:27
+#define NVC56F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000
+#define NVC56F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001
+#define NVC56F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002
+#define NVC56F_SEM_EXECUTE_REDUCTION_IAND 0x00000003
+#define NVC56F_SEM_EXECUTE_REDUCTION_IOR 0x00000004
+#define NVC56F_SEM_EXECUTE_REDUCTION_IADD 0x00000005
+#define NVC56F_SEM_EXECUTE_REDUCTION_INC 0x00000006
+#define NVC56F_SEM_EXECUTE_REDUCTION_DEC 0x00000007
+#define NVC56F_SEM_EXECUTE_REDUCTION_FORMAT 31:31
+#define NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000
+#define NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001
+#define NVC56F_WFI (0x00000078)
+#define NVC56F_WFI_SCOPE 0:0
+#define NVC56F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000
+#define NVC56F_WFI_SCOPE_CURRENT_VEID 0x00000000
+#define NVC56F_WFI_SCOPE_ALL 0x00000001
+#define NVC56F_YIELD (0x00000080)
+#define NVC56F_YIELD_OP 1:0
+#define NVC56F_YIELD_OP_NOP 0x00000000
+#define NVC56F_YIELD_OP_TSG 0x00000003
+#define NVC56F_CLEAR_FAULTED (0x00000084)
+// Note: RM provides the HANDLE as an opaque value; the internal detail fields
+// are intentionally not exposed to the driver through these defines.
+#define NVC56F_CLEAR_FAULTED_HANDLE 30:0
+#define NVC56F_CLEAR_FAULTED_TYPE 31:31
+#define NVC56F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000
+#define NVC56F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001
+
+
+/* GPFIFO entry format */
+#define NVC56F_GP_ENTRY__SIZE 8
+#define NVC56F_GP_ENTRY0_FETCH 0:0
+#define NVC56F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
+#define NVC56F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
+#define NVC56F_GP_ENTRY0_GET 31:2
+#define NVC56F_GP_ENTRY0_OPERAND 31:0
+#define NVC56F_GP_ENTRY1_GET_HI 7:0
+#define NVC56F_GP_ENTRY1_LEVEL 9:9
+#define NVC56F_GP_ENTRY1_LEVEL_MAIN 0x00000000
+#define NVC56F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
+#define NVC56F_GP_ENTRY1_LENGTH 30:10
+#define NVC56F_GP_ENTRY1_SYNC 31:31
+#define NVC56F_GP_ENTRY1_SYNC_PROCEED 0x00000000
+#define NVC56F_GP_ENTRY1_SYNC_WAIT 0x00000001
+#define NVC56F_GP_ENTRY1_OPCODE 7:0
+#define NVC56F_GP_ENTRY1_OPCODE_NOP 0x00000000
+#define NVC56F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
+#define NVC56F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
+#define NVC56F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
+
+/* dma method formats */
+#define NVC56F_DMA_METHOD_ADDRESS_OLD 12:2
+#define NVC56F_DMA_METHOD_ADDRESS 11:0
+#define NVC56F_DMA_SUBDEVICE_MASK 15:4
+#define NVC56F_DMA_METHOD_SUBCHANNEL 15:13
+#define NVC56F_DMA_TERT_OP 17:16
+#define NVC56F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
+#define NVC56F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
+#define NVC56F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
+#define NVC56F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
+#define NVC56F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
+#define NVC56F_DMA_METHOD_COUNT_OLD 28:18
+#define NVC56F_DMA_METHOD_COUNT 28:16
+#define NVC56F_DMA_IMMD_DATA 28:16
+#define NVC56F_DMA_SEC_OP 31:29
+#define NVC56F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
+#define NVC56F_DMA_SEC_OP_INC_METHOD (0x00000001)
+#define NVC56F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
+#define NVC56F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
+#define NVC56F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
+#define NVC56F_DMA_SEC_OP_ONE_INC (0x00000005)
+#define NVC56F_DMA_SEC_OP_RESERVED6 (0x00000006)
+#define NVC56F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
+/* dma incrementing method format */
+#define NVC56F_DMA_INCR_ADDRESS 11:0
+#define NVC56F_DMA_INCR_SUBCHANNEL 15:13
+#define NVC56F_DMA_INCR_COUNT 28:16
+#define NVC56F_DMA_INCR_OPCODE 31:29
+#define NVC56F_DMA_INCR_OPCODE_VALUE (0x00000001)
+#define NVC56F_DMA_INCR_DATA 31:0
+/* dma non-incrementing method format */
+#define NVC56F_DMA_NONINCR_ADDRESS 11:0
+#define NVC56F_DMA_NONINCR_SUBCHANNEL 15:13
+#define NVC56F_DMA_NONINCR_COUNT 28:16
+#define NVC56F_DMA_NONINCR_OPCODE 31:29
+#define NVC56F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
+#define NVC56F_DMA_NONINCR_DATA 31:0
+/* dma increment-once method format */
+#define NVC56F_DMA_ONEINCR_ADDRESS 11:0
+#define NVC56F_DMA_ONEINCR_SUBCHANNEL 15:13
+#define NVC56F_DMA_ONEINCR_COUNT 28:16
+#define NVC56F_DMA_ONEINCR_OPCODE 31:29
+#define NVC56F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
+#define NVC56F_DMA_ONEINCR_DATA 31:0
+/* dma no-operation format */
+#define NVC56F_DMA_NOP (0x00000000)
+/* dma immediate-data format */
+#define NVC56F_DMA_IMMD_ADDRESS 11:0
+#define NVC56F_DMA_IMMD_SUBCHANNEL 15:13
+#define NVC56F_DMA_IMMD_DATA 28:16
+#define NVC56F_DMA_IMMD_OPCODE 31:29
+#define NVC56F_DMA_IMMD_OPCODE_VALUE (0x00000004)
+/* dma set sub-device mask format */
+#define NVC56F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
+/* dma store sub-device mask format */
+#define NVC56F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
+#define NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
+/* dma use sub-device mask format */
+#define NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
+/* dma end-segment format */
+#define NVC56F_DMA_ENDSEG_OPCODE 31:29
+#define NVC56F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
+/* dma legacy incrementing/non-incrementing formats */
+#define NVC56F_DMA_ADDRESS 12:2
+#define NVC56F_DMA_SUBCH 15:13
+#define NVC56F_DMA_OPCODE3 17:16
+#define NVC56F_DMA_OPCODE3_NONE (0x00000000)
+#define NVC56F_DMA_COUNT 28:18
+#define NVC56F_DMA_OPCODE 31:29
+#define NVC56F_DMA_OPCODE_METHOD (0x00000000)
+#define NVC56F_DMA_OPCODE_NONINC_METHOD (0x00000002)
+#define NVC56F_DMA_DATA 31:0
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _clc56f_h_ */
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _clc76f_h_
+#define _clc76f_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nvtypes.h"
+
+/* class AMPERE_CHANNEL_GPFIFO */
+/*
+ * Documentation for AMPERE_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
+ * chapter "User Control Registers". It is documented as device NV_UDMA.
+ * The GPFIFO format itself is also documented in dev_pbdma.ref,
+ * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
+ * chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
+ *
+ * Note there is no .mfs file for this class.
+ */
+#define AMPERE_CHANNEL_GPFIFO_B (0x0000C76F)
+
+#define NVC76F_TYPEDEF AMPERE_CHANNELChannelGPFifoB
+
+/* dma flow control data structure */
+typedef volatile struct Nvc76fControl_struct {
+ NvU32 Ignored00[0x010]; /* 0000-003f*/
+ NvU32 Put; /* put offset, read/write 0040-0043*/
+ NvU32 Get; /* get offset, read only 0044-0047*/
+ NvU32 Reference; /* reference value, read only 0048-004b*/
+ NvU32 PutHi; /* high order put offset bits 004c-004f*/
+ NvU32 Ignored01[0x002]; /* 0050-0057*/
+ NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
+ NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
+ NvU32 GetHi; /* high order get offset bits 0060-0063*/
+ NvU32 Ignored02[0x007]; /* 0064-007f*/
+ NvU32 Ignored03; /* used to be engine yield 0080-0083*/
+ NvU32 Ignored04[0x001]; /* 0084-0087*/
+ NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
+ NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
+ NvU32 Ignored05[0x5c];
+} Nvc76fControl, AmpereAControlGPFifo;
+
+/* fields and values */
+#define NVC76F_NUMBER_OF_SUBCHANNELS (8)
+#define NVC76F_SET_OBJECT (0x00000000)
+#define NVC76F_SET_OBJECT_NVCLASS 15:0
+#define NVC76F_SET_OBJECT_ENGINE 20:16
+#define NVC76F_SET_OBJECT_ENGINE_SW 0x0000001f
+#define NVC76F_ILLEGAL (0x00000004)
+#define NVC76F_ILLEGAL_HANDLE 31:0
+#define NVC76F_NOP (0x00000008)
+#define NVC76F_NOP_HANDLE 31:0
+#define NVC76F_SEMAPHOREA (0x00000010)
+#define NVC76F_SEMAPHOREA_OFFSET_UPPER 7:0
+#define NVC76F_SEMAPHOREB (0x00000014)
+#define NVC76F_SEMAPHOREB_OFFSET_LOWER 31:2
+#define NVC76F_SEMAPHOREC (0x00000018)
+#define NVC76F_SEMAPHOREC_PAYLOAD 31:0
+#define NVC76F_SEMAPHORED (0x0000001C)
+#define NVC76F_SEMAPHORED_OPERATION 4:0
+#define NVC76F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
+#define NVC76F_SEMAPHORED_OPERATION_RELEASE 0x00000002
+#define NVC76F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
+#define NVC76F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008
+#define NVC76F_SEMAPHORED_OPERATION_REDUCTION 0x00000010
+#define NVC76F_SEMAPHORED_ACQUIRE_SWITCH 12:12
+#define NVC76F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000
+#define NVC76F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001
+#define NVC76F_SEMAPHORED_RELEASE_WFI 20:20
+#define NVC76F_SEMAPHORED_RELEASE_WFI_EN 0x00000000
+#define NVC76F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001
+#define NVC76F_SEMAPHORED_RELEASE_SIZE 24:24
+#define NVC76F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000
+#define NVC76F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001
+#define NVC76F_SEMAPHORED_REDUCTION 30:27
+#define NVC76F_SEMAPHORED_REDUCTION_MIN 0x00000000
+#define NVC76F_SEMAPHORED_REDUCTION_MAX 0x00000001
+#define NVC76F_SEMAPHORED_REDUCTION_XOR 0x00000002
+#define NVC76F_SEMAPHORED_REDUCTION_AND 0x00000003
+#define NVC76F_SEMAPHORED_REDUCTION_OR 0x00000004
+#define NVC76F_SEMAPHORED_REDUCTION_ADD 0x00000005
+#define NVC76F_SEMAPHORED_REDUCTION_INC 0x00000006
+#define NVC76F_SEMAPHORED_REDUCTION_DEC 0x00000007
+#define NVC76F_SEMAPHORED_FORMAT 31:31
+#define NVC76F_SEMAPHORED_FORMAT_SIGNED 0x00000000
+#define NVC76F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001
+#define NVC76F_NON_STALL_INTERRUPT (0x00000020)
+#define NVC76F_NON_STALL_INTERRUPT_HANDLE 31:0
+#define NVC76F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR
+#define NVC76F_FB_FLUSH_HANDLE 31:0
+// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
+// specifying the page address for a targeted TLB invalidate and the uTLB for
+// a targeted REPLAY_CANCEL for UVM.
+// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly
+// rearranged fields.
+#define NVC76F_MEM_OP_A (0x00000028)
+#define NVC76F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED
+#define NVC76F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type
+#define NVC76F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED
+#define NVC76F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE 7:6 // only relevant for invalidates with NVC76F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE for invalidating link TLB only, or non-link TLB only or all TLBs
+#define NVC76F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS 0
+#define NVC76F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS 1
+#define NVC76F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 2
+#define NVC76F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD 3
+#define NVC76F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL
+#define NVC76F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11
+#define NVC76F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001
+#define NVC76F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000
+#define NVC76F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12
+#define NVC76F_MEM_OP_B (0x0000002c)
+#define NVC76F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0
+#define NVC76F_MEM_OP_C (0x00000030)
+#define NVC76F_MEM_OP_C_MEMBAR_TYPE 2:0
+#define NVC76F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000
+#define NVC76F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003
+#define NVC76F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE
+#define NVC76F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0
+// MEM_OP_D MUST be preceded by MEM_OPs A-C.
+#define NVC76F_MEM_OP_D (0x00000034)
+#define NVC76F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE
+#define NVC76F_MEM_OP_D_OPERATION 31:27
+#define NVC76F_MEM_OP_D_OPERATION_MEMBAR 0x00000005
+#define NVC76F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009
+#define NVC76F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a
+#define NVC76F_MEM_OP_D_OPERATION_MMU_OPERATION 0x0000000b
+#define NVC76F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
+#define NVC76F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
+// CLEAN_LINES is an alias for Tegra/GPU IP usage
+#define NVC76F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e
+#define NVC76F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
+#define NVC76F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010
+#define NVC76F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015
+#define NVC76F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016
+#define NVC76F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0
+#define NVC76F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000
+#define NVC76F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001
+#define NVC76F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002
+#define NVC76F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003
+#define NVC76F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2
+#define NVC76F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000
+#define NVC76F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001
+#define NVC76F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3
+#define NVC76F_MEM_OP_D_MMU_OPERATION_TYPE 23:20
+#define NVC76F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED 0x00000000
+#define NVC76F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP 0x00000001
+#define NVC76F_SET_REFERENCE (0x00000050)
+#define NVC76F_SET_REFERENCE_COUNT 31:0
+#define NVC76F_SEM_ADDR_LO (0x0000005c)
+#define NVC76F_SEM_ADDR_LO_OFFSET 31:2
+#define NVC76F_SEM_ADDR_HI (0x00000060)
+#define NVC76F_SEM_ADDR_HI_OFFSET 7:0
+#define NVC76F_SEM_PAYLOAD_LO (0x00000064)
+#define NVC76F_SEM_PAYLOAD_LO_PAYLOAD 31:0
+#define NVC76F_SEM_PAYLOAD_HI (0x00000068)
+#define NVC76F_SEM_PAYLOAD_HI_PAYLOAD 31:0
+#define NVC76F_SEM_EXECUTE (0x0000006c)
+#define NVC76F_SEM_EXECUTE_OPERATION 2:0
+#define NVC76F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000
+#define NVC76F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
+#define NVC76F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002
+#define NVC76F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003
+#define NVC76F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004
+#define NVC76F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005
+#define NVC76F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006
+#define NVC76F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12
+#define NVC76F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000
+#define NVC76F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001
+#define NVC76F_SEM_EXECUTE_RELEASE_WFI 20:20
+#define NVC76F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
+#define NVC76F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001
+#define NVC76F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
+#define NVC76F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
+#define NVC76F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001
+#define NVC76F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25
+#define NVC76F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000
+#define NVC76F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001
+#define NVC76F_SEM_EXECUTE_REDUCTION 30:27
+#define NVC76F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000
+#define NVC76F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001
+#define NVC76F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002
+#define NVC76F_SEM_EXECUTE_REDUCTION_IAND 0x00000003
+#define NVC76F_SEM_EXECUTE_REDUCTION_IOR 0x00000004
+#define NVC76F_SEM_EXECUTE_REDUCTION_IADD 0x00000005
+#define NVC76F_SEM_EXECUTE_REDUCTION_INC 0x00000006
+#define NVC76F_SEM_EXECUTE_REDUCTION_DEC 0x00000007
+#define NVC76F_SEM_EXECUTE_REDUCTION_FORMAT 31:31
+#define NVC76F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000
+#define NVC76F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001
+#define NVC76F_WFI (0x00000078)
+#define NVC76F_WFI_SCOPE 0:0
+#define NVC76F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000
+#define NVC76F_WFI_SCOPE_CURRENT_VEID 0x00000000
+#define NVC76F_WFI_SCOPE_ALL 0x00000001
+#define NVC76F_YIELD (0x00000080)
+#define NVC76F_YIELD_OP 1:0
+#define NVC76F_YIELD_OP_NOP 0x00000000
+#define NVC76F_YIELD_OP_TSG 0x00000003
+#define NVC76F_CLEAR_FAULTED (0x00000084)
+// Note: RM provides the HANDLE as an opaque value; the internal detail fields
+// are intentionally not exposed to the driver through these defines.
+#define NVC76F_CLEAR_FAULTED_HANDLE 30:0
+#define NVC76F_CLEAR_FAULTED_TYPE 31:31
+#define NVC76F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000
+#define NVC76F_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001
+
+
+/* GPFIFO entry format */
+#define NVC76F_GP_ENTRY__SIZE 8
+#define NVC76F_GP_ENTRY0_FETCH 0:0
+#define NVC76F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
+#define NVC76F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
+#define NVC76F_GP_ENTRY0_GET 31:2
+#define NVC76F_GP_ENTRY0_OPERAND 31:0
+#define NVC76F_GP_ENTRY1_GET_HI 7:0
+#define NVC76F_GP_ENTRY1_LEVEL 9:9
+#define NVC76F_GP_ENTRY1_LEVEL_MAIN 0x00000000
+#define NVC76F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
+#define NVC76F_GP_ENTRY1_LENGTH 30:10
+#define NVC76F_GP_ENTRY1_SYNC 31:31
+#define NVC76F_GP_ENTRY1_SYNC_PROCEED 0x00000000
+#define NVC76F_GP_ENTRY1_SYNC_WAIT 0x00000001
+#define NVC76F_GP_ENTRY1_OPCODE 7:0
+#define NVC76F_GP_ENTRY1_OPCODE_NOP 0x00000000
+#define NVC76F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
+#define NVC76F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
+#define NVC76F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
+
+/* dma method formats */
+#define NVC76F_DMA_METHOD_ADDRESS_OLD 12:2
+#define NVC76F_DMA_METHOD_ADDRESS 11:0
+#define NVC76F_DMA_SUBDEVICE_MASK 15:4
+#define NVC76F_DMA_METHOD_SUBCHANNEL 15:13
+#define NVC76F_DMA_TERT_OP 17:16
+#define NVC76F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000)
+#define NVC76F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001)
+#define NVC76F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002)
+#define NVC76F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003)
+#define NVC76F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000)
+#define NVC76F_DMA_METHOD_COUNT_OLD 28:18
+#define NVC76F_DMA_METHOD_COUNT 28:16
+#define NVC76F_DMA_IMMD_DATA 28:16
+#define NVC76F_DMA_SEC_OP 31:29
+#define NVC76F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000)
+#define NVC76F_DMA_SEC_OP_INC_METHOD (0x00000001)
+#define NVC76F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002)
+#define NVC76F_DMA_SEC_OP_NON_INC_METHOD (0x00000003)
+#define NVC76F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004)
+#define NVC76F_DMA_SEC_OP_ONE_INC (0x00000005)
+#define NVC76F_DMA_SEC_OP_RESERVED6 (0x00000006)
+#define NVC76F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007)
+/* dma incrementing method format */
+#define NVC76F_DMA_INCR_ADDRESS 11:0
+#define NVC76F_DMA_INCR_SUBCHANNEL 15:13
+#define NVC76F_DMA_INCR_COUNT 28:16
+#define NVC76F_DMA_INCR_OPCODE 31:29
+#define NVC76F_DMA_INCR_OPCODE_VALUE (0x00000001)
+#define NVC76F_DMA_INCR_DATA 31:0
+/* dma non-incrementing method format */
+#define NVC76F_DMA_NONINCR_ADDRESS 11:0
+#define NVC76F_DMA_NONINCR_SUBCHANNEL 15:13
+#define NVC76F_DMA_NONINCR_COUNT 28:16
+#define NVC76F_DMA_NONINCR_OPCODE 31:29
+#define NVC76F_DMA_NONINCR_OPCODE_VALUE (0x00000003)
+#define NVC76F_DMA_NONINCR_DATA 31:0
+/* dma increment-once method format */
+#define NVC76F_DMA_ONEINCR_ADDRESS 11:0
+#define NVC76F_DMA_ONEINCR_SUBCHANNEL 15:13
+#define NVC76F_DMA_ONEINCR_COUNT 28:16
+#define NVC76F_DMA_ONEINCR_OPCODE 31:29
+#define NVC76F_DMA_ONEINCR_OPCODE_VALUE (0x00000005)
+#define NVC76F_DMA_ONEINCR_DATA 31:0
+/* dma no-operation format */
+#define NVC76F_DMA_NOP (0x00000000)
+/* dma immediate-data format */
+#define NVC76F_DMA_IMMD_ADDRESS 11:0
+#define NVC76F_DMA_IMMD_SUBCHANNEL 15:13
+#define NVC76F_DMA_IMMD_DATA 28:16
+#define NVC76F_DMA_IMMD_OPCODE 31:29
+#define NVC76F_DMA_IMMD_OPCODE_VALUE (0x00000004)
+/* dma set sub-device mask format */
+#define NVC76F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4
+#define NVC76F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC76F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001)
+/* dma store sub-device mask format */
+#define NVC76F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4
+#define NVC76F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC76F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002)
+/* dma use sub-device mask format */
+#define NVC76F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16
+#define NVC76F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003)
+/* dma end-segment format */
+#define NVC76F_DMA_ENDSEG_OPCODE 31:29
+#define NVC76F_DMA_ENDSEG_OPCODE_VALUE (0x00000007)
+/* dma legacy incrementing/non-incrementing formats */
+#define NVC76F_DMA_ADDRESS 12:2
+#define NVC76F_DMA_SUBCH 15:13
+#define NVC76F_DMA_OPCODE3 17:16
+#define NVC76F_DMA_OPCODE3_NONE (0x00000000)
+#define NVC76F_DMA_COUNT 28:18
+#define NVC76F_DMA_OPCODE 31:29
+#define NVC76F_DMA_OPCODE_METHOD (0x00000000)
+#define NVC76F_DMA_OPCODE_NONINC_METHOD (0x00000002)
+#define NVC76F_DMA_DATA 31:0
+
+#ifdef __cplusplus
+}; /* extern "C" */
+#endif
+
+#endif /* _clc76f_h_ */
dirs = {
'/classes/compute/': 'classes/',
'/classes/dma-copy/': 'classes/',
+ '/classes/host/': 'classes/',
'/classes/memory-to-memory-format/': 'classes/',
'/classes/twod/': 'classes/',
}
projects / platform / upstream / mesa.git / commitdiff