drm/i915/perf: Add 32-bit OAG and OAR formats for DG2

Add new OA formats for DG2.

MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893

v2:
- Update commit title (Ashutosh)
- Coding style fixes (Lionel)
- 64 bit OA formats need UMD changes in GPUvis, drop for now and send in a
  separate series with UMD changes

v3:
- Update commit message to drop 64 bit related description

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> #1
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221026222102.5526-3-umesh.nerlige.ramappa@intel.com

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2553358..2b772a6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -320,6 +320,8 @@ static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = {
        [I915_OA_FORMAT_A12]                = { 0, 64 },
        [I915_OA_FORMAT_A12_B8_C8]          = { 2, 128 },
        [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
+       [I915_OAR_FORMAT_A32u40_A4u32_B8_C8]    = { 5, 256 },
+       [I915_OA_FORMAT_A24u40_A14u32_B8_C8]    = { 5, 256 },
 };
 
 #define SAMPLE_OA_REPORT      (1<<0)
@@ -4515,6 +4517,11 @@ static void oa_init_supported_formats(struct i915_perf *perf)
                oa_format_add(perf, I915_OA_FORMAT_C4_B8);
                break;
 
+       case INTEL_DG2:
+               oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
+               oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
+               break;
+
        default:
                MISSING_CASE(platform);
        }

diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 08d69e3..b946674 100644 (file)
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2666,6 +2666,10 @@ enum drm_i915_oa_format {
        I915_OA_FORMAT_A12_B8_C8,
        I915_OA_FORMAT_A32u40_A4u32_B8_C8,
 
+       /* DG2 */
+       I915_OAR_FORMAT_A32u40_A4u32_B8_C8,
+       I915_OA_FORMAT_A24u40_A14u32_B8_C8,
+
        I915_OA_FORMAT_MAX          /* non-ABI */
 };