con |= pdata->reference_voltage << reg->buf_vref_sel_shift;
}
- /*
- * In Exynos 4x12 and 5250,
- * MUX bits should be set to 0x6 for normal operation.
- * For ohters, it can be ignored.
- */
- if (pdata->type == SOC_ARCH_EXYNOS) {
- con &= ~(EXYNOS_TMU_MUX_ADDR_MASK << EXYNOS_TMU_MUX_ADDR_SHIFT);
- con |= EXYNOS_TMU_MUX_ADDR_DEFAULT << EXYNOS_TMU_MUX_ADDR_SHIFT;
- }
-
if (pdata->gain) {
con &= ~(reg->buf_slope_sel_mask << reg->buf_slope_sel_shift);
con |= (pdata->gain << reg->buf_slope_sel_shift);
#define EXYNOS_TMU_TEMP_MASK 0xff
#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
#define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
-#define EXYNOS_TMU_MUX_ADDR_DEFAULT 0x6
-#define EXYNOS_TMU_MUX_ADDR_MASK 0x7
-#define EXYNOS_TMU_MUX_ADDR_SHIFT 20
#define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
#define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
#define EXYNOS_TMU_CORE_EN_SHIFT 0