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clk: at91: allow 24 Mhz clock as input for PLL
author
Eugen Hristev
<eugen.hristev@microchip.com>
Wed, 11 Sep 2019 06:39:20 +0000
(06:39 +0000)
committer
Stephen Boyd
<sboyd@kernel.org>
Wed, 18 Sep 2019 05:00:31 +0000
(22:00 -0700)
The PLL input range needs to be able to allow 24 Mhz crystal as input
Update the range accordingly in plla characteristics struct
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link:
https://lkml.kernel.org/r/1568183622-7858-1-git-send-email-eugen.hristev@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Fixes:
c561e41ce4d2
("clk: at91: add sama5d2 PMC driver")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/at91/sama5d2.c
patch
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diff --git
a/drivers/clk/at91/sama5d2.c
b/drivers/clk/at91/sama5d2.c
index
6509d09
..
0de1108
100644
(file)
--- a/
drivers/clk/at91/sama5d2.c
+++ b/
drivers/clk/at91/sama5d2.c
@@
-21,7
+21,7
@@
static const struct clk_range plla_outputs[] = {
};
static const struct clk_pll_characteristics plla_characteristics = {
- .input = { .min = 12000000, .max =
12
000000 },
+ .input = { .min = 12000000, .max =
24
000000 },
.num_output = ARRAY_SIZE(plla_outputs),
.output = plla_outputs,
.icpll = plla_icpll,