};
static const struct omap_video_timings tvc_pal_timings = {
- .x_res = 720,
+ .hactive = 720,
.y_res = 574,
.pixelclock = 13500000,
.hsw = 64,
#include "../dss/omapdss.h"
static const struct omap_video_timings dvic_default_timings = {
- .x_res = 640,
+ .hactive = 640,
.y_res = 480,
.pixelclock = 23500000,
#include "../dss/omapdss.h"
static const struct omap_video_timings hdmic_default_timings = {
- .x_res = 640,
+ .hactive = 640,
.y_res = 480,
.pixelclock = 25175000,
.hsw = 96,
static void dsicm_get_resolution(struct omap_dss_device *dssdev,
u16 *xres, u16 *yres)
{
- *xres = dssdev->panel.timings.x_res;
+ *xres = dssdev->panel.timings.hactive;
*yres = dssdev->panel.timings.y_res;
}
/* XXX no need to send this every frame, but dsi break if not done */
r = dsicm_set_update_window(ddata, 0, 0,
- dssdev->panel.timings.x_res,
+ dssdev->panel.timings.hactive,
dssdev->panel.timings.y_res);
if (r)
goto err;
}
size = min(w * h * 3,
- dssdev->panel.timings.x_res *
+ dssdev->panel.timings.hactive *
dssdev->panel.timings.y_res * 3);
in->ops.dsi->bus_lock(in);
if (r)
return r;
- ddata->timings.x_res = 864;
+ ddata->timings.hactive = 864;
ddata->timings.y_res = 480;
ddata->timings.pixelclock = 864 * 480 * 60;
#include "../dss/omapdss.h"
static struct omap_video_timings lb035q02_timings = {
- .x_res = 320,
+ .hactive = 320,
.y_res = 240,
.pixelclock = 6500000,
};
static const struct omap_video_timings nec_8048_panel_timings = {
- .x_res = LCD_XRES,
+ .hactive = LCD_XRES,
.y_res = LCD_YRES,
.pixelclock = LCD_PIXEL_CLOCK,
.hfp = 6,
};
static const struct omap_video_timings sharp_ls_timings = {
- .x_res = 480,
+ .hactive = 480,
.y_res = 640,
.pixelclock = 19200000,
};
static const struct omap_video_timings acx565akm_panel_timings = {
- .x_res = 800,
+ .hactive = 800,
.y_res = 480,
.pixelclock = 24000000,
.hfp = 28,
};
static struct omap_video_timings td028ttec1_panel_timings = {
- .x_res = 480,
+ .hactive = 480,
.y_res = 640,
.pixelclock = 22153000,
.hfp = 24,
};
static const struct omap_video_timings tpo_td043_timings = {
- .x_res = 800,
+ .hactive = 800,
.y_res = 480,
.pixelclock = 36000000,
u64 val, blank;
int i;
- nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
+ nonactive = t->hactive + t->hfp + t->hsw + t->hbp - out_width;
i = 0;
if (out_height < height)
return (unsigned long) pclk;
if (height > out_height) {
- unsigned int ppl = mgr_timings->x_res;
+ unsigned int ppl = mgr_timings->hactive;
tmp = (u64)pclk * height * out_width;
do_div(tmp, 2 * out_height * ppl);
const u8 zorder = 0, global_alpha = 0;
const bool replication = false;
bool truncation;
- int in_width = mgr_timings->x_res;
+ int in_width = mgr_timings->hactive;
int in_height = mgr_timings->y_res;
enum omap_overlay_caps caps =
OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
bool dispc_mgr_timings_ok(enum omap_channel channel,
const struct omap_video_timings *timings)
{
- if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
+ if (!_dispc_mgr_size_ok(timings->hactive, timings->y_res))
return false;
if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
unsigned long ht, vt;
struct omap_video_timings t = *timings;
- DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
+ DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.y_res);
if (!dispc_mgr_timings_ok(channel, &t)) {
BUG();
t.vfp, t.vbp, t.vsync_level, t.hsync_level,
t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
- xtot = t.x_res + t.hfp + t.hsw + t.hbp;
+ xtot = t.hactive + t.hfp + t.hsw + t.hbp;
ytot = t.y_res + t.vfp + t.vsw + t.vbp;
ht = timings->pixelclock / xtot;
19, 17);
}
- dispc_mgr_set_size(channel, t.x_res, t.y_res);
+ dispc_mgr_set_size(channel, t.hactive, t.y_res);
}
EXPORT_SYMBOL(dispc_mgr_set_timings);
struct dss_lcd_mgr_config lcd_conf;
} i734 = {
.timings = {
- .x_res = 8, .y_res = 1,
+ .hactive = 8, .y_res = 1,
.pixelclock = 16000000,
.hsw = 8, .hfp = 4, .hbp = 4,
.vsw = 1, .vfp = 1, .vbp = 1,
void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
u16 *xres, u16 *yres)
{
- *xres = dssdev->panel.timings.x_res;
+ *xres = dssdev->panel.timings.hactive;
*yres = dssdev->panel.timings.y_res;
}
EXPORT_SYMBOL(omapdss_default_get_resolution);
memset(ovt, 0, sizeof(*ovt));
ovt->pixelclock = vm->pixelclock;
- ovt->x_res = vm->hactive;
+ ovt->hactive = vm->hactive;
ovt->hbp = vm->hback_porch;
ovt->hfp = vm->hfront_porch;
ovt->hsw = vm->hsync_len;
vm->pixelclock = ovt->pixelclock;
- vm->hactive = ovt->x_res;
+ vm->hactive = ovt->hactive;
vm->hback_porch = ovt->hbp;
vm->hfront_porch = ovt->hfp;
vm->hsync_len = ovt->hsw;
struct dpi_clk_calc_ctx ctx;
bool ok;
- if (timings->x_res % 8 != 0)
+ if (timings->hactive % 8 != 0)
return -EINVAL;
if (!dispc_mgr_timings_ok(channel, timings))
* Don't use line buffers if width is greater than the video
* port's line buffer size
*/
- if (dsi->line_buffer_size <= timings->x_res * bpp / 8)
+ if (dsi->line_buffer_size <= timings->hactive * bpp / 8)
num_line_buffers = 0;
else
num_line_buffers = 2;
exiths_clk = ths_exit + tclk_trail;
- width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
+ width_bytes = DIV_ROUND_UP(timings->hactive * bpp, 8);
bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
if (!hsa_blanking_mode) {
t_he = hsync_end ?
((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
- width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
+ width_bytes = DIV_ROUND_UP(timings->hactive * bpp, 8);
/* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
/* MODE, 1 = video mode */
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
- word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
+ word_count = DIV_ROUND_UP(dsi->timings.hactive * bpp, 8);
dsi_vc_write_long_header(dsidev, channel, data_type,
word_count, 0);
int r;
const unsigned channel = dsi->update_channel;
const unsigned line_buf_size = dsi->line_buffer_size;
- u16 w = dsi->timings.x_res;
+ u16 w = dsi->timings.hactive;
u16 h = dsi->timings.y_res;
DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
dsi->framedone_callback = callback;
dsi->framedone_data = data;
- dw = dsi->timings.x_res;
+ dw = dsi->timings.hactive;
dh = dsi->timings.y_res;
#ifdef DSI_PERF_MEASURE
unsigned long pck = t->pixelclock;
int hact, bl, tot;
- hact = t->x_res;
+ hact = t->hactive;
bl = t->hsw + t->hbp + t->hfp;
tot = hact + bl;
vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
- vm.x_res = t->hact;
+ vm.hactive = t->hact;
print_dispc_vm(str, &vm);
}
*t = *ctx->config->timings;
t->pixelclock = pck;
- t->x_res = ctx->config->timings->x_res;
+ t->hactive = ctx->config->timings->hactive;
t->y_res = ctx->config->timings->y_res;
t->hsw = t->hfp = t->hbp = t->vsw = 1;
t->vfp = t->vbp = 0;
dispc_pck = ctx->dispc_cinfo.pck;
dispc_tput = (u64)dispc_pck * bitspp;
- xres = req_vm->x_res;
+ xres = req_vm->hactive;
panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
panel_htot = xres + panel_hbl;
p = &hdmi.cfg.timings;
- DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
+ DSSDBG("hdmi_power_on hactive= %d y_res = %d\n", p->hactive, p->y_res);
pc = p->pixelclock;
if (p->double_pixel)
p = &hdmi.cfg.timings;
- DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
+ DSSDBG("hdmi_power_on hactive= %d y_res = %d\n", p->hactive, p->y_res);
pc = p->pixelclock;
if (p->double_pixel)
}
if (cfg->timings.double_pixel) {
- video_cfg->v_fc_config.timings.x_res *= 2;
+ video_cfg->v_fc_config.timings.hactive *= 2;
video_cfg->hblank *= 2;
video_cfg->v_fc_config.timings.hfp *= 2;
video_cfg->v_fc_config.timings.hsw *= 2;
/* set x resolution */
REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1,
- cfg->v_fc_config.timings.x_res >> 8, 4, 0);
+ cfg->v_fc_config.timings.hactive >> 8, 4, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0,
- cfg->v_fc_config.timings.x_res & 0xFF, 7, 0);
+ cfg->v_fc_config.timings.hactive & 0xFF, 7, 0);
/* set y resolution */
REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1,
video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
video_fmt->y_res = param->timings.y_res;
- video_fmt->x_res = param->timings.x_res;
+ video_fmt->x_res = param->timings.hactive;
timings->hbp = param->timings.hbp;
timings->hfp = param->timings.hfp;
struct omap_video_timings {
/* Unit: pixels */
- u16 x_res;
+ u16 hactive;
/* Unit: pixels */
u16 y_res;
/* Unit: Hz */
u32 l;
int r;
struct omap_overlay_manager *mgr = rfbi.output.manager;
- u16 width = rfbi.timings.x_res;
+ u16 width = rfbi.timings.hactive;
u16 height = rfbi.timings.y_res;
/*BUG_ON(callback == 0);*/
static void rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h)
{
- rfbi.timings.x_res = w;
+ rfbi.timings.hactive = w;
rfbi.timings.y_res = h;
}
dss_mgr_set_lcd_config(mgr, &mgr_config);
/*
- * Set rfbi.timings with default values, the x_res and y_res fields
+ * Set rfbi.timings with default values, the hactive and y_res fields
* are expected to be already configured by the panel driver via
* omapdss_rfbi_set_size()
*/
};
const struct omap_video_timings omap_dss_pal_timings = {
- .x_res = 720,
+ .hactive = 720,
.y_res = 574,
.pixelclock = 13500000,
.hsw = 64,
EXPORT_SYMBOL(omap_dss_pal_timings);
const struct omap_video_timings omap_dss_ntsc_timings = {
- .x_res = 720,
+ .hactive = 720,
.y_res = 482,
.pixelclock = 13500000,
.hsw = 64,
{
mode->clock = timings->pixelclock / 1000;
- mode->hdisplay = timings->x_res;
+ mode->hdisplay = timings->hactive;
mode->hsync_start = mode->hdisplay + timings->hfp;
mode->hsync_end = mode->hsync_start + timings->hsw;
mode->htotal = mode->hsync_end + timings->hbp;
{
timings->pixelclock = mode->clock * 1000;
- timings->x_res = mode->hdisplay;
+ timings->hactive = mode->hdisplay;
timings->hfp = mode->hsync_start - mode->hdisplay;
timings->hsw = mode->hsync_end - mode->hsync_start;
timings->hbp = mode->htotal - mode->hsync_end;