let UnsupportedFeatures = Arch11UnsupportedFeatures.List;
- let IssueWidth = 6; // 2 * 3 instructions decoded per cycle.
+ let IssueWidth = 8;
let MicroOpBufferSize = 60; // Issue queues
let LoadLatency = 1; // Optimistic load latency.
let UnsupportedFeatures = Arch9UnsupportedFeatures.List;
- let IssueWidth = 3; // 3 instructions decoded per cycle.
+ let IssueWidth = 5;
let MicroOpBufferSize = 40; // Issue queues
let LoadLatency = 1; // Optimistic load latency.
def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
// Execution units.
-def Z196_FXUnit : ProcResource<1>;
-def Z196_LSUnit : ProcResource<1>;
+def Z196_FXUnit : ProcResource<2>;
+def Z196_LSUnit : ProcResource<2>;
def Z196_FPUnit : ProcResource<1>;
// Subtarget specific definitions of scheduling resources.
let UnsupportedFeatures = Arch10UnsupportedFeatures.List;
- let IssueWidth = 3; // 3 instructions decoded per cycle.
+ let IssueWidth = 5;
let MicroOpBufferSize = 40; // Issue queues
let LoadLatency = 1; // Optimistic load latency.
def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
// Execution units.
-def ZEC12_VBUnit : ProcResource<1>;
-def ZEC12_FXUnit : ProcResource<1>;
-def ZEC12_LSUnit : ProcResource<1>;
+def ZEC12_FXUnit : ProcResource<2>;
+def ZEC12_LSUnit : ProcResource<2>;
def ZEC12_FPUnit : ProcResource<1>;
+def ZEC12_VBUnit : ProcResource<1>;
// Subtarget specific definitions of scheduling resources.
def : WriteRes<FXU, [ZEC12_FXUnit]> { let Latency = 1; }