pa.md (sh[123]add patterns): Use register_operand, not shadd_operand.

	* pa.md (sh[123]add patterns): Use register_operand, not
	shadd_operand.
	(sh[123]add patterns for reload): Special patterns to avoid
	lossage due to reload problems.

From-SVN: r3737

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 56a84b6..0f220c8 100644 (file)
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -2250,13 +2250,11 @@
   [(set_attr "type" "load")
    (set_attr "length" "1")])
 
-;; Using shadd_operand works around a bug in reload.  For 2.4 fix
-;; reload and use register_operand instead.
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
        (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
                          (const_int 2))
-                (match_operand:SI 1 "shadd_operand" "r")))]
+                (match_operand:SI 1 "register_operand" "r")))]
   ""
   "sh1add %2,%1,%0")
 
@@ -2264,7 +2262,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
        (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
                          (const_int 4))
-                (match_operand:SI 1 "shadd_operand" "r")))]
+                (match_operand:SI 1 "register_operand" "r")))]
   ""
   "sh2add %2,%1,%0")
 
@@ -2272,10 +2270,47 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
        (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
                          (const_int 8))
-                (match_operand:SI 1 "shadd_operand" "r")))]
+                (match_operand:SI 1 "register_operand" "r")))]
   ""
   "sh3add %2,%1,%0")
 
+;; These variants of the above insns can occur if the first operand
+;; is the frame pointer.  This is a kludge, but there doesn't
+;; seem to be a way around it.  Only recognize them while reloading.
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=&r")
+       (plus:SI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
+                                  (const_int 2))
+                         (match_operand:SI 1 "register_operand" "r"))
+                (match_operand:SI 3 "const_int_operand" "rJ")))]
+  "reload_in_progress"
+  "sh1add  %2,%1,%0\\n\\tadd%I3 %3,%0,%0"
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=&r")
+       (plus:SI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
+                                  (const_int 4))
+                         (match_operand:SI 1 "register_operand" "r"))
+                (match_operand:SI 3 "const_int_operand" "rJ")))]
+  "reload_in_progress"
+  "sh2add  %2,%1,%0\\n\\tadd%I3 %3,%0,%0"
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=&r")
+       (plus:SI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
+                                  (const_int 8))
+                         (match_operand:SI 1 "register_operand" "r"))
+                (match_operand:SI 3 "const_int_operand" "rJ")))]
+  "reload_in_progress"
+  "sh3add  %2,%1,%0\\n\\tadd%I3 %3,%0,%0"
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
+
 (define_expand "ashlsi3"
   [(set (match_operand:SI 0 "register_operand" "")
        (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")