bool ism6_0Imm() const { return CheckImmRange(6, 0, false, false, false); }
bool isn8_0Imm() const { return CheckImmRange(8, 0, false, false, false); }
+ bool isn1Const() const {
+ if (!isImm())
+ return false;
+ int64_t Value;
+ if (!getImm()->evaluateAsAbsolute(Value))
+ return false;
+ return Value == -1;
+ }
bool iss16_0Ext() const { return CheckImmRange(16 + 26, 0, true, true, true); }
bool iss12_0Ext() const { return CheckImmRange(12 + 26, 0, true, true, true); }
void adds11_3ExtOperands(MCInst &Inst, unsigned N) const {
addSignedImmOperands(Inst, N);
}
+ void addn1ConstOperands(MCInst &Inst, unsigned N) const {
+ addImmOperands(Inst, N);
+ }
void addu7_0ExtOperands(MCInst &Inst, unsigned N) const {
addImmOperands(Inst, N);
}
}
+ switch(MI.getOpcode()) {
+ case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
+ case Hexagon::J4_cmpeqn1_f_jumpnv_t:
+ case Hexagon::J4_cmpeqn1_fp0_jump_nt:
+ case Hexagon::J4_cmpeqn1_fp0_jump_t:
+ case Hexagon::J4_cmpeqn1_fp1_jump_nt:
+ case Hexagon::J4_cmpeqn1_fp1_jump_t:
+ case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
+ case Hexagon::J4_cmpeqn1_t_jumpnv_t:
+ case Hexagon::J4_cmpeqn1_tp0_jump_nt:
+ case Hexagon::J4_cmpeqn1_tp0_jump_t:
+ case Hexagon::J4_cmpeqn1_tp1_jump_nt:
+ case Hexagon::J4_cmpeqn1_tp1_jump_t:
+ case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
+ case Hexagon::J4_cmpgtn1_f_jumpnv_t:
+ case Hexagon::J4_cmpgtn1_fp0_jump_nt:
+ case Hexagon::J4_cmpgtn1_fp0_jump_t:
+ case Hexagon::J4_cmpgtn1_fp1_jump_nt:
+ case Hexagon::J4_cmpgtn1_fp1_jump_t:
+ case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
+ case Hexagon::J4_cmpgtn1_t_jumpnv_t:
+ case Hexagon::J4_cmpgtn1_tp0_jump_nt:
+ case Hexagon::J4_cmpgtn1_tp0_jump_t:
+ case Hexagon::J4_cmpgtn1_tp1_jump_nt:
+ case Hexagon::J4_cmpgtn1_tp1_jump_t:
+ MI.insert(MI.begin() + 1, MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
+ break;
+ default:
+ break;
+ }
+
if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
MCOperand &MCO = MI.getOperand(OpIndex);
// with a register and an hardcoded 0/-1 immediate value.
//===----------------------------------------------------------------------===//
-let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
+let isExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
opExtentAlign = 2 in
class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
bit isNegCond, bit isTak>
: NVInst_V4<(outs),
- (ins IntRegs:$src1, brtarget:$offset),
+ !if(!eq(ImmVal, "{-1}"),
+ (ins IntRegs:$src1, n1Const:$n1, brtarget:$offset),
+ (ins IntRegs:$src1, brtarget:$offset)),
"if ("#!if(isNegCond, "!","")#mnemonic
#"($src1.new, #" # ImmVal # ")) jump:"
#!if(isTak, "t","nt")#" $offset", []> {
let isTaken = isTak;
let isPredicatedFalse = isNegCond;
let isTaken = isTak;
+ let opExtendable = !if(!eq(ImmVal, "{-1}"), 2, 1);
bits<3> src1;
bits<11> offset;
let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
Defs = [PC], hasSideEffects = 0 in {
defm J4_tstbit0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
- defm J4_cmpeqn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
- defm J4_cmpgtn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
+ defm J4_cmpeqn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "{-1}">, PredRel;
+ defm J4_cmpgtn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "{-1}">, PredRel;
}
// J4_hintjumpr: Hint indirect conditional jump.
let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1,
- isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
+ isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 2,
isTerminator = 1 in
class CJInst_Rn1<string px, string op, bit np, string tnt>
- : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
- ""#px#" = cmp."#op#"($Rs,#-1); if ("
+ : InstHexagon<(outs), (ins IntRegs:$Rs, n1Const:$n1, brtarget:$r9_2),
+ ""#px#" = cmp."#op#"($Rs,#$n1); if ("
#!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
[], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon {
bits<4> Rs;